P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
2.3.2 Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1 EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]#
S_HPREQ#
High Priority Request pre-empts the low priority request.
© 1998 Zarlink Semiconductor, Inc.
16
Rev. 2.1- February, 1999