P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
2.2.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
ꢁ
This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation.
These registers are reserved for system diagnostic usage only.
ꢂ
I/O Offset
Register
Description
Little Big
Endian Endian
Reg.
Size
W/R
Note:
Device Configuration Registers (DCR)
GCR
Global Control Register
hF00
hF02
16-bit
W/--
ꢁ
DCR0
DCR1
DCR2
DCR3
DCR4
DTSR
Device Status Register
Signature & Revision Register
ID Register
hF00
hF10
hF20
hF30
hF40
hF70
hF02
hF12
hF22
hF32
hF42
hF72
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/R
--/R
W/R
Device Configuration Register
Interfaces Status Register
Test Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
hF80
hF90
hFA0
hFB0
hF82
hF92
hFA2
hFB2
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/--
ISRM
IMSK
IAR
Interrupt Status Register – Masked
Interrupt Mask Register
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR
MRAR
MBAR
MWBS
MRBS
MWDR
MWDX
MRDR
MRDX
Memory Write Address Reg. – Single Cycle
hE08
hE18
hE28
hE40
hE50
hE68
hE6C
hE68
hE6C
hE08
hE18
hE28
hE42
hE52
hE68
hE6C
hE68
hE6C
32-bit
32-bit
32-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
W/R
W/R
W/R
W/R
W/R
W/--
W/--
--/R
Memory Read Address Reg. – Single Cycle
Memory Address Register – Burst Mode
Memory Write Burst Size (in D-words)
Memory Read Burst Size (in D-words)
Memory Write Data Register
Memory Write Data Reg. – Byte Swapping
Memory Read Data Register
Memory Read Data Reg. – Byte Swapping
--/R
FCB Buffer & Stack Management
FCBBA
FCBAG
Frame Control Buffer – Base Address
hD00
hD30
hD02
hD32
16-bit
16-bit
W/R
--/R
Frame Control Buffer – Buffer Aging Status
ꢂ
ꢂ
FCBSL
FCBST
FCBSS
Frame Ctrl Buffer Stack – Size Limit
hD90
hDA0
hDB0
hD92
hDA2
hDB2
16-bit
16-bit
16-bit
W/R
W/R
--/R
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
© 1998 Zarlink Semiconductor, Inc.
13
Rev. 2.1- February, 1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
