P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
I/O Offset
Register
Description
Little Big
Endian Endian
Reg.
Size
W/R
Note:
Access Control Function (Chip Level controls)
AVXR
VLAN Control Table (VCT) Index Register
VCT Data Register
hC00
hC10
hC20
hC30
hC40
hC40
hC70
hC80
hC90
hCA0
hCB0
hCC0
hCD0
hCE0
hC02
hC12
hC22
hC32
hC40
hC40
hC72
hC82
hC92
hCA2
hCB2
hCC2
hCD2
hCE2
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/--
W/R
W/R
W/R
W/--
--/R
AVDR
AVTC
VLAN Type Code
AXSC
Transmission Scheduling Control Register
MII Command Register
AMIIC
AMIIS
MII Status Register
AFCR
Flow Control Register
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
AMAR0
AMAR1
AMAR2
AMCT
ADAR0
ADAR1
ADAR2
Multicast Address. for MAC Control Frames
Byte [3,2]
Byte [1,0]
Byte [5,4]
MAC Control FrameType Code Register
Base MAC Address Register – Byte [1,0]
Base MAC Address Register – Byte [3,2]
Base MAC Address Register – Byte [5,4]
Ethernet MAC Port Control Registers – (substitute [n] with Port Number, n = {0..3] )
ECR0
ECR1
ECR2
ECR3
EXSR
EXEC
ERSR
EREC
MAC Port Control Register
MAC Port Configuration Register
MAC Port Interrupt Mask Register
MAC Port Interrupt Status Register
MAC Tx Status Register
hn00
hn10
hn20
hn30
hn40
hn50
hn68
hn78
hn02
hn12
hn22
hn32
hn42
hn52
hn68
hn78
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
W/R
W/R
W/R
--/R
--/R
--/R
--/R
--/R
ꢂ
ꢂ
ꢂ
ꢂ
MAC Tx Error Counters
MAC Rx Status Register
MAC Rx Error Counters
© 1998 Zarlink Semiconductor, Inc.
14
Rev. 2.1- February, 1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
