P
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E
L
I
M
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N
A
R
Y
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F
O
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M
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T
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XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
2.2 Processor Bus Interface
ꢀ Supports various industry standard micro-processors including:
ꢀ Supports 16-bit Data Bus
ꢀ Supports early RDY cycle
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Intel 186, 386, and 486 family or equivalent
Motorola MPC series embedded processors
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Meets timing requirement for Intel/AMD 186 family proc-
essors
ꢀ Easily adapts to other industry standard CPUs
ꢀ Provides separate Address and Data bus
ꢀ Supports Big & Little Endian byte ordering
ꢀ Supports 1X or 2X CPU Clock
2X CPU Clock for 386 family processors
ꢀ Provides a single interrupt signal to Switch Manager CPU
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2.2.1 Pin Description
Symbol
P_C[4:0]
Type
Name and Functions
CMOS Input
Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the
processor configuration. By using external weak pull-up or -down resistors, they define the Ex-
ternal Management Bus Interface Configuration. These inputs are sampled at the trailing edge of
the Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and
the setting of this bit is ignored.
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
C[0]
C[1]
C[2]
C[3]
C[4]
CPU Clock
Byte Order
RWC
Bus Size
RDY Timing
Lo
Hi
1X Clock
2x Clock
Little Endian
Big Endian
P_R/W#
P_W/R#
n/a
n/a
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Address Bus Bit [11:1] – I/O port address
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
TTL In (5VT)
TTL I/O-TS (5VT) Data Bus Bit [15:0] – a 16-bit synchronous data bus.
TTL In (5VT) Address Strobe – indicates valid address is on the bus
TTL Input (5VT) Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low
C[1]=High
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
P_RDY#
P_BS16#
P_CS#
TTL Out-OD
TTL Out-OD
Data Ready – timing indicates for bus data valid
Bus Size 16 – response to bus master that the EA208 only supports 16-bit data bus width.
TTL Input (5VT) Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
CMOS Output
ꢁ
Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable
via chip configuration register.
P_INT
P_RST#
P_CLK
TTL In-ST (5VT) CPU Reset – Synchronous reset Input from Switch Manager CPU
TTL In (5VT)
CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
© 1998 Zarlink Semiconductor, Inc.
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Rev. 2.1- February, 1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
