YMF724F
4-4. AC’97 / AC3F2 Master Clock (Fig.5)
Item
Symbol
Min.
Typ.
Max.
Unit
CMCLK Cycle Time
CMCLK High Time
CMCLK Low Time
CMCLK Rising Time
CMCLK Falling Time
tCMCYC
tCMHIGH
tCMLOW
tCMR
-
8
8
-
40.69
-
-
-
-
-
-
ns
ns
ns
ns
ns
4.6
2.1
tCMF
-
Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
t
t
CMR
CMF
3.5 V
2.5 V
0.4 V
CMCLK
t
t
CMHIGH
t
CMLOW
CMCYC
Fig.5: Master Clock timing for AC’97 and AC3F2
4-5. AC-link (Fig.6)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
CBCLK Cycle Time
tCBICYC
tCBIHIGH
tCBILOW
tCSYCYC
tCSYHIGH
tCSYLOW
tCVAL
-
35
35
-
81.4
40.7
40.7
20.8
1.3
19.5
-
-
45
45
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CBCLK High Time
CBCLK Low Time
CSYNC Cycle Time
CSYNC High Time
-
-
CSYNC Low Time
-
-
CBCLK to Signal Valid Delay
Output Hold Time for CBCLK
Input Setup Time to CBCLK
Input Hold Time for CBCLK
Warm Reset Width
*12
*12
*13
*13
-
20
-
tCOH
0
-
tCISU
15
5
-
-
tCIH
-
-
-
1.3
-
Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
*12: This characteristic is applicable to CSYNC and CSDO signal.
*13: This characteristic is applicable to CSDI signal.
January 14, 1999
-46-
YAMAHA [ YAMAHA CORPORATION ]
