R
Spartan-II FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination. The four global clock pins are usable as additional user I/Os when not used as a global clock
pin. These pins are not included in user I/O counts.
Table 2: Spartan-II FPGA User I/O Chart(1)
Available User I/O According to Package Type
Maximum
User I/O
VQ100
VQG100
TQ144
TQG144
CS144
CSG144
PQ208
PQG208
FG256
FGG256
FG456
FGG456
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
86
92
60
60
-
86
92
92
92
-
(Note 2)
-
(Note 2)
140
-
-
92
-
-
-
-
176
176
260
284
176
176
176
176
-
-
140
(Note 2)
260
-
-
140
-
-
-
140
284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
2. Discontinued by PDN2004-01.
DS001-1 (v2.8) June 13, 2008
Product Specification
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