R
Spartan-II FPGA Family: Functional Description
support of a wide variety of applications, from general
purpose standard applications to high-speed low-voltage
memory busses.
Table 15: Versatile I/O Supported Standards (Typical
Values)
Input
Reference Source Termination
Voltage Voltage Voltage
Output
Board
Versatile I/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL
output buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak "keeper" circuit ideal for
use in external bussing applications.
I/O Standard
LVTTL (2-24 mA)
LVCMOS2
(VREF
)
(VCCO
)
(VTT
N/A
N/A
N/A
)
N/A
3.3
N/A
2.5
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
PCI (3V/5V,
N/A
3.3
33 MHz/66 MHz)
GTL
0.8
1.0
N/A
N/A
1.5
1.5
1.5
3.3
1.2
1.5
The input buffer has an optional delay element used to
guarantee a zero hold time requirement for input signals
registered within the IOB.
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
0.75
0.9
0.9
0.75
1.5
1.5
The Versatile I/O features also provide dedicated resources
for input reference voltage (VREF) and output source
voltage (VCCO), along with a convenient banking system
that simplifies board design.
SSTL3 Class I
and II
1.5
1.5
By taking advantage of the built-in features and wide variety
of I/O standards supported by the Versatile I/O features,
system-level design and board design can be greatly
simplified and improved.
SSTL2 Class I
and II
1.25
2.5
1.25
CTT
1.5
3.3
3.3
1.5
Fundamentals
AGP-2X
1.32
N/A
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored
specifically to the needs of that application. The bus I/O
standards provide specifications to other vendors who
create products designed to interface with these
applications. Each standard often has its own specifications
for current, voltage, I/O buffering, and termination
techniques.
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Spartan-II devices.
While most I/O standards specify a range of allowed
voltages, this document records typical voltage values only.
Detailed information on each specification may be found on
the Electronic Industry Alliance JEDEC website at
http://www.jedec.org. For more details on the I/O standards
and termination application examples, see XAPP179, "Using
SelectIO Interfaces in Spartan-II and Spartan-IIE FPGAs."
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly
dependent on the capability of the programmable logic
device to support an ever increasing variety of I/O
standards
LVTTL — Low-Voltage TTL
The Low-Voltage TTL (LVTTL) standard is a general
purpose EIA/JESDSA standard for 3.3V applications that
uses an LVTTL input buffer and a Push-Pull output buffer.
This standard requires a 3.3V output source voltage
(VCCO), but does not require the use of a reference voltage
(VREF) or a termination voltage (VTT).
The Versatile I/O resources feature highly configurable
input and output buffers which provide support for a wide
variety of I/O standards. As shown in Table 15, each buffer
type can support a variety of voltage requirements.
LVCMOS2 — Low-Voltage CMOS for 2.5V
The Low-Voltage CMOS for 2.5V or lower (LVCMOS2)
standard is an extension of the LVCMOS standard (JESD
8.5) used for general purpose 2.5V applications. This
standard requires a 2.5V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
board termination voltage (VTT).
DS001-2 (v2.8) June 13, 2008
Product Specification
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