R
Spartan-II FPGA Family: Functional Description
T
T
BPWL
BPWH
CLK
T
T
BACK
00
ADDR
0F
7E
8F
BDCK
DDDD
CCCC
BBBB
2222
DIN
DOUT
EN
T
BCKO
MEM (00)
CCCC
MEM (7E)
T
BECK
RST
WE
T
BWCK
DISABLED
READ
WRITE
READ
DISABLED
DS001_33_061200
Figure 33: Timing Diagram for Single-Port Block RAM Memory
T
BCCS
VIOLATION
CLK_A
ADDR_A
00
7E
0F
0F
7E
EN_A
WE_A
DI_A
T
BCCS
T
BCCS
AAAA
9999
AAAA
0000
1111
AAAA
9999
AAAA
UNKNOWN
2222
DO_A
CLK_B
ADDR_B
00
00
7E
0F
0F
7E
1A
EN_B
WE_B
DI_B
1111
1111
1111
BBBB
1111
2222
FFFF
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
DS001_34_061200
Figure 34: Timing Diagram for a True Dual-Port Read/Write Block RAM Memory
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 2 of 4
35
XILINX [ XILINX, INC ]
