R
Spartan-II FPGA Family: Functional Description
the DI bus. The DI bus is written to the memory location
0x0F.
Creating Larger RAM Structures
The block RAM columns have specialized routing to allow
cascading blocks together with minimal routing delays. This
achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
Location Constraints
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block RAM memory is now disabled. The
DO bus retains the last value.
Block RAM instances can have LOC properties attached to
them to constrain the placement. The block RAM placement
locations are separate from the CLB location naming
convention, allowing the LOC properties to transfer easily
from array to array.
Dual Port Timing
The LOC properties use the following form:
LOC = RAMB4_R#C#
Figure 34 shows a timing diagram for a true dual-port
read/write block RAM memory. The clock on port A has a
longer period than the clock on Port B. The timing
parameter TBCCS, (clock-to-clock setup) is shown on this
diagram. The parameter, TBCCS is violated once in the
diagram. All other timing parameters are identical to the
single port version shown in Figure 33.
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Conflict Resolution
The block RAM memory is a true dual-read/write port RAM
that allows simultaneous access of the same memory cell
from both ports. When one port writes to a given memory
cell, the other port must not address that memory cell (for a
write or a read) within the clock-to-clock setup window. The
following lists specifics of port and memory cell write conflict
resolution.
TBCCS is only of importance when the address of both ports
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is
violated for a WRITE-WRITE condition, the contents of the
memory at that location will be invalid. When the
clock-to-clock set-up parameter is violated for a
WRITE-READ condition, the contents of the memory will be
correct, but the read port will have invalid data. At the first
rising edge of the CLKA, memory location 0x00 is to be
written with the value 0xAAAA and is mirrored on the DOA
bus. The last operation of Port B was a read to the same
memory location 0x00. The DOB bus of Port B does not
change with the new value on Port A, and retains the last
read value. A short time later, Port B executes another read
to memory location 0x00, and the DOB bus now reflects the
new memory value written by Port A.
•
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
•
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
-
The data out on the reading port is invalid.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the TBCCS parameter and
the DOB reflects the new memory values written by Port A.
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block
RAM memory. The block RAM AC switching characteristics
are specified in the data sheet. The block RAM memory is
initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus
contains the contents of the memory location, 0x00, as
indicated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors
DS001-2 (v2.8) June 13, 2008
Product Specification
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