R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and are expressed in nano-
seconds unless otherwise noted.
Speed Grade
-5
-4
(1)
Symbol
Single Port RAM
Size
Min
Max
Min
Max
Units
Write Operation
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
7.7
7.7
3.1
3.1
1.3
1.5
1.5
1.8
1.4
1.3
0.0
-
-
8.4
8.4
3.6
3.6
1.5
1.7
1.7
2.1
1.6
1.5
0.0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCS
T
-
-
WCTS
T
-
-
WPS
T
-
-
WPTS
T
-
-
ASS
T
-
-
ASTS
T
-
-
DSS
T
-
-
-
-
DSTS
T
WE setup time before clock K
WSS
T
-
-
WSTS
All hold times after clock K
Data valid after clock K
-
-
T
4.5
5.4
5.3
6.3
WOS
T
-
-
WOTS
Read Operation
T
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
-
3.1
5.5
-
-
-
ns
ns
ns
ns
ns
ns
RC
T
RCT
T
Data Valid after address change (no Write
Enable)
1.0
1.7
-
1.1
2.0
-
ILO
T
-
-
IHO
T
Address setup time before clock K
0.6
1.3
0.7
1.6
ICK
T
-
-
IHCK
Notes:
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
56
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
