R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Setup Times
T
T
Clock Enable (EC) to Clock (IK)
All devices
All devices
All devices
0.0
1.0
0.7
-
-
-
0.0
1.2
0.8
-
-
-
ns
ns
ns
ECIK
PICK
Pad to Clock (IK), no delay
T
Pad to Fast Capture Latch Enable (OK), no delay
POCK
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
T
Pad to I1, I2
All devices
All devices
All devices
All devices
-
-
-
-
0.9
2.1
1.0
1.1
-
-
-
-
1.1
2.5
1.1
1.2
ns
ns
ns
ns
PID
T
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
PLI
T
IKRI
T
Clock (IK) to I1, I2 (latch enable, active Low)
IKLI
Delay Adder for Input with Full Delay Option
T
T
T
= T
+ T
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.0
4.8
5.0
5.5
6.5
-
-
-
-
-
4.7
5.6
5.9
6.5
7.6
-
-
-
-
-
ns
ns
ns
ns
ns
Delay
PICKD
PICK
Delay
+ T
Delay
= T
PDLI
PLI
Global Set/Reset
T
Minimum GSR pulse width
All devices 10.5
-
11.5
-
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Q
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
-
-
-
-
-
9.0
-
-
-
-
-
10.5
11.0
11.5
12.5
13.5
RRI
9.5
10.0
11.0
12.0
Notes:
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
60
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
