R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and expressed in nanosec-
onds unless otherwise noted.
Speed Grade
-5
-4
Symbol
Clocks
Description
Min
Max
Min
Max
Units
T
Clock High time
Clock Low time
2.0
2.0
-
-
2.3
2.3
-
-
ns
ns
CH
T
CL
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
-
1.0
1.7
1.5
1.5
-
-
-
-
1.1
2.0
1.8
1.8
ns
ns
ns
ns
ILO
T
F/G inputs via H to X/Y outputs
IHO
T
F/G inputs via transparent latch to Q outputs
C inputs via H1 via H to X/Y outputs
ITO
T
HH1O
Sequential Delays
Clock K to Flip-Flop or latch outputs Q
Setup Time before Clock K
T
-
1.2
-
1.4
ns
CKO
T
F/G inputs
0.6
1.3
-
-
0.7
1.6
-
-
ns
ns
ICK
T
F/G inputs via H
IHCK
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
0.0
-
0.0
-
ns
T
Width (High)
2.5
-
-
2.8
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
2.3
2.7
RIO
Global Set/Reset
T
T
Minimum GSR Pulse Width
10.5
-
11.5
-
ns
MRW
Delay from GSR input to any Q
See page 60 for T
values per device.
RRI
MRQ
F
Toggle Frequency (MHz)
-
250
-
217
MHz
TOG
(for export control purposes)
DS060 (v1.6) September 19, 2001
Product Specification
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