R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
Speed Grade
-5
Max
1.4
1.7
2.0
2.3
2.6
-4
Max
1.5
1.8
2.1
2.5
2.8
Symbol
Description
Device
Units
ns
T
From pad through buffer, to any clock K
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
GLS
ns
ns
ns
ns
54
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DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
