R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values are
expressed in nanoseconds unless otherwise noted.
Speed Grade
-4
-3
Symbol
Clocks
Description
Device
Min
Max
Min
Max
Units
T
Clock High
Clock Low
All devices
All devices
3.0
3.0
-
-
4.0
4.0
-
-
ns
ns
CH
T
CL
Propagation Delays - TTL Outputs(1,2)
T
Clock (OK) to Pad, fast
All devices
All devices
All devices
All devices
All devices
All devices
All devices
-
-
-
-
-
-
-
3.3
6.9
3.6
7.2
3.0
6.0
9.6
-
-
-
-
-
-
-
4.5
7.0
4.8
7.3
3.8
7.3
9.8
ns
ns
ns
ns
ns
ns
ns
OKPOF
T
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
OKPOS
T
OPF
T
Output (O) to Pad, slew-rate limited
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
OPS
T
TSHZ
TSONF
TSONS
T
T
Setup and Hold Times
T
T
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
All devices
All devices
All devices
All devices
2.5
0.0
2.0
0.0
-
-
-
-
3.8
0.0
2.7
0.5
-
-
-
-
ns
ns
ns
ns
OOK
OKO
T
T
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
ECOK
OKEC
Global Set/Reset
T
Minimum GSR pulse width
All devices
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
13.5
ns
ns
ns
ns
ns
ns
MRW
T
Delay from GSR input to any Pad
-
-
-
-
-
12.0
12.5
13.0
13.5
14.0
-
-
-
-
-
15.0
15.7
16.2
16.9
17.5
RPO
Notes:
1. Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
2. Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
3. Output timing is measured at ~50% V threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
CC
rise/fall times are approximately two times longer than fast output rise/fall times.
4. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
DS060 (v1.6) September 19, 2001
www.xilinx.com
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Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
