R
Platform Flash In-System Programmable Configuration PROMS
T
CKMIN
TCK
T
MSS
T
MSH
TMS
T
DIS
T
DIH
TDI
T
DOV
TDO
DS026_04_020300
Figure 6:
Test Access Port Timing
TAP AC Parameters
shows the timing parameters for the TAP waveforms shown in
Table 8:
Test Access Port Timing Parameters
Symbol
T
CKMIN
T
MSS
T
MSH
T
DIS
T
DIH
T
DOV
Description
TCK minimum clock period when V
CCJ
= 2.5V or 3.3V
TMS setup time when V
CCJ
= 2.5V or 3.3V
TMS hold time when V
CCJ
= 2.5V or 3.3V
TDI setup time when V
CCJ
= 2.5V or 3.3V
TDI hold time when V
CCJ
= 2.5V or 3.3V
TDO valid delay when V
CCJ
= 2.5V or 3.3V
Min
100
10
25
10
25
-
Max
-
-
-
-
-
30
Units
ns
ns
ns
ns
ns
ns
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
an optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled during device pro-
gramming, and can be set to either the default frequency or
to a slower frequency (AC
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. When dis-
abled, the CLKOUT pin is put into a high-impedance state
and should be pulled High externally to provide a known
state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and releases the CEO pin enabling the
next PROM in the PROM chain. The next PROM will begin
driving the CLKOUT signal once that PROM is enabled and
data is available for transfer.
During high-speed parallel configuration without compres-
sion, the FPGA drives the BUSY signal on the configuration
interface. When BUSY is asserted High, the PROMs inter-
nal address counter stops incrementing, and the current
data value is held on the data outputs. While BUSY is High,
the PROM will continue driving the CLKOUT signal to the
FPGA, clocking the FPGA’s configuration logic. When the
FPGA deasserts BUSY, indicating that it is ready to receive
additional configuration data, the PROM will begin driving
new data onto the configuration interface.
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
the programmable option to enable the CLKOUT signal
which allows the PROM to provide a source synchronous
clock aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources:
the CLK input pin or the internal oscillator. The input clock
source is selected during the PROM programming
sequence. Output data is available on the rising edge of
CLKOUT.
DS123 (v2.6) March 14, 2005
Preliminary Product Specification
8
XILINX [ XILINX, INC ]
