R
Platform Flash In-System Programmable Configuration PROMS
programming data sequence is delivered to the device
using either Xilinx iMPACT software and a Xilinx download
cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format, including
automatic test equipment. During in-system programming,
the CEO output is driven High. All other outputs are held in
a high-impedance state or held at clamp levels during
in-system programming. In-system programming is fully
supported across the recommended operating voltage and
temperature ranges.
Table 2:
Xilinx FPGAs and Compatible Platform Flash
PROMs
(Continued)
FPGA
Spartan-3
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
439,264
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
630,048
863,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
197,696
336,768
559,200
781,216
1,040,096
1,335,840
XCF01S
XCF01S
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
XCF01S
XCF01S
XCF02S
XCF02S
XCF02S
XCF04S
XCF04S
XCF01S
XCF01S
XCF01S
XCF01S
XCF01S
XCF02S
Configuration
Bitstream
Platform Flash
PROM
(1)
Spartan-IIE
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
V
CC
GND
Spartan-II
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
(a)
(b)
DS026_02_082703
Figure 3:
JTAG In-System Programming Operation
(a) Solder Device to PCB
(b) Program Using Download Cable
OE/RESET
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system
programming algorithm results in issuance of an internal
device reset that causes OE/RESET to pulse Low.
Notes:
1. If design revisioning or other advanced feature support is required,
the XCFxxP can be used as an alternative to the XCF01S, XCF02S,
or XCF04S.
2. Assumes compression used.
3. The largest possible Virtex-II bitstream sizes are specified. Refer to
the Virtex-II User Guide for information on bitgen options which
affect bitstream size.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx MultiPRO Desktop Tool or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Table 3:
Platform Flash PROM Capacity
Platform
Flash PROM
Configuration
Bits
Platform Flash
PROM
Configuration
Bits
XCF01S
XCF02S
XCF04S
1,048,576
2,097,152
4,194,304
XCF08P
XCF16P
XCF32P
8,388,608
16,777,216
33,554,432
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Programming
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together
and programmed in-system via the standard 4-pin JTAG
protocol as shown in
In-system programming
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices. The
DS123 (v2.6) March 14, 2005
Preliminary Product Specification
Design Security
The Xilinx in-system programmable Platform Flash PROM
devices incorporate advanced data security features to fully
protect the FPGA programming data against unauthorized
reading via JTAG. The XCFxxP PROMs can also be pro-
4
XILINX [ XILINX, INC ]
