R
Platform Flash In-System Programmable Configuration PROMS
PROM 0
REV 0
(8 Mbits)
PROM 0
REV 0
(8 Mbits)
PROM 0
PROM 0
REV 0
(8 Mbits)
PROM 0
REV 0
(16 Mbits)
REV 1
(8 Mbits)
REV 1
(8 Mbits)
REV 0
(32 Mbits)
REV 2
(8 Mbits)
REV 2
(16 Mbits)
REV 3
(8 Mbits)
REV 1
(16 Mbits)
REV 1
(24 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM
PROM 0
REV 0
(16 Mbits)
PROM 0
REV 0
(16 Mbits)
REV 0
(32 Mbits)
REV 1
(16 Mbits)
REV 1
(16 Mbits)
REV 1
(16 Mbits)
PROM 0
PROM 0
REV 0
(16 Mbits)
REV 0
(32 Mbits)
PROM 0
PROM 1
REV 2
(16 Mbits)
PROM 1
PROM 1
PROM 1
PROM 1
REV 2
(32 Mbits)
REV 3
(16 Mbits)
REV 1
(32 Mbits)
REV 1
(32 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
ds123_20_102103
(b) Design Revision storage examples spanning two XCF32P PROMs
Figure 7:
Design Revision Storage Examples
PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal interconnec-
tions are established by the configuration data contained in
the FPGA’s bitstream. The bitstream is loaded into the
FPGA either automatically upon power up, or on command,
depending on the state of the FPGA's mode pins. Xilinx
Platform Flash PROMs are designed to download directly to
the FPGA configuration interface. FPGA configuration
modes which are supported by the XCFxxS Platform Flash
PROMs include: Master Serial and Slave Serial. FPGA con-
figuration modes which are supported by the XCFxxP Plat-
form Flash PROMs include: Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP. Below is a short
summary of the supported FPGA configuration modes. See
the respective FPGA data sheet for device configuration
details, including which configuration modes are supported
by the targeted FPGA device.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external mem-
ory synchronized by the configuration clock (CCLK) gener-
ated by the FPGA. Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is incre-
mented on every valid rising edge of CCLK. The serial bit-
stream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
DS123 (v2.6) March 14, 2005
Preliminary Product Specification
XILINX [ XILINX, INC ]
