R
Platform Flash In-System Programmable Configuration PROMS
it contains logic "0". The DONE field, IR[2], contains logic
"1" if the sampled design revision has been successfully
programmed; otherwise, a logic "0" indicates incomplete
programming. The remaining bits IR[1:0] are set to '01' as
defined by IEEE Std. 1149.1
.
erwise a "01" when an erase or program operation fails. The
Erase/Program (ER/PROG) Status field, IR[4], contains a
logic "1" when the device is busy performing an erase or
programming operation; otherwise, it contains a logic "0".
The ISC Status field, IR[3], contains logic "1" if the device is
currently in In-System Configuration (ISC) mode; otherwise,
Table 6:
Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command
Required Instructions
BYPASS
SAMPLE/PRELOAD
EXTEST
Optional Instructions
CLAMP
HIGHZ
IDCODE
USERCODE
Platform Flash PROM Specific
Instructions
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)
(1)
XCFxxS IR[7:0]
(hex)
XCFxxP IR[15:0]
(hex)
Instruction Description
FF
01
00
FFFF
0001
0000
Enables BYPASS
Enables boundary-scan SAMPLE/PRELOAD operation
Enables boundary-scan EXTEST operation
FA
FC
FE
FD
00FA
00FC
00FE
00FD
Enables boundary-scan CLAMP operation
Places all outputs in high-impedance state
simultaneously
Enables shifting out 32-bit IDCODE
Enables shifting out 32-bit USERCODE
CONFIG
EE
00EE
Notes:
1. For more information see Initiating FPGA Configuration.
TDI
→
IR[7:5]
Reserved
IR[4]
ISC Status
IR[3]
Security
IR[2]
0
IR[1:0]
01
→
TDO
Figure 4:
XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
IR[15:9]
TDI
→
Reserved
IR[8:7]
ISC Error
IR[6:5]
ER/PROG
Error
IR[4]
ER/PROG
Status
IR[3]
ISC Status
IR[2]
DONE
IR[1:0]
01
→
TDO
Figure 5:
XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the Platform Flash PROM has two register stages which
contribute to the boundary-scan register, while each input
pin has only one register stage. The bidirectional pins have
a total of three register stages which contribute to the
boundary-scan register. For each output pin, the register
stage nearest to TDI controls and observes the output state,
and the second stage closest to TDO controls and observes
the High-Z enable state of the output pin. For each input pin,
a single register stage controls and observes the input state
of the pin. The bidirectional pin combines the three bits, the
input stage bit is first, followed by the output stage bit and
finally the output enable stage bit. The output enable stage
bit is closest to TDO.
DS123 (v2.6) March 14, 2005
Preliminary Product Specification
6
XILINX [ XILINX, INC ]
