Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 46: Clock-Capable Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC
/
Nodelayclock-capable XC7A12T
2.68/–0.19 3.04/–0.19 3.64/–0.19
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.68/–0.19 3.04/–0.19 3.64/–0.19
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.78/–0.20 3.15/–0.20 3.78/–0.20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.64/–0.19 2.32/–0.57
3.77/–0.20 2.46/–0.59
3.64/–0.19 2.32/–0.57
3.77/–0.20 2.46/–0.59
3.77/–0.20 2.46/–0.59
3.78/–0.20 2.47/–0.59
3.78/–0.20 2.47/–0.59
3.94/–0.21 2.64/–0.62
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHPLLCC clock input and IFF(2)
with PLL
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T 2.78/–0.20 3.15/–0.20 3.78/–0.20
XC7A200T 2.91/–0.21 3.29/–0.21 3.94/–0.21
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.04/–0.19 3.64/–0.19 3.64/–0.19
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.04/–0.19 3.64/–0.19 3.64/–0.19
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.15/–0.20 3.77/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20 3.78/–0.20
3.29/–0.21 3.94/–0.21 3.94/–0.21 3.94/–0.21
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS
Setup and hold of I/O clock
–0.38/1.31 –0.38/1.46 –0.38/1.76 –0.38/1.76 –0.38/1.76 –0.16/1.89
ns
Table 48: Sample Window
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.64
0.95V
-1LI
0.9V
-2LE
0.70
Units
-3
-1
-1M/-1Q
TSAMP
Sampling error at receiver pins(1)
0.59
0.70
0.70
0.70
ns
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
47
XILINX [ XILINX, INC ]
