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XC6VLX75T-1FFG484C 参数 Datasheet PDF下载

XC6VLX75T-1FFG484C图片预览
型号: XC6VLX75T-1FFG484C
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1098MHz, 74496-Cell, CMOS, PBGA484, 23 X 23 MM, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 65 页 / 1429 K
品牌: XILINX [ XILINX, INC ]
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics  
Virtex-6 Device Pin-to-Pin Input Parameter Guidelines  
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are  
listed in Table 68. Values are expressed in nanoseconds unless otherwise noted.  
Table 68: Global Clock Input Setup and Hold Without MMCM  
Speed Grade  
Symbol  
Description  
Device  
Units  
-3  
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)  
-2  
-1  
-1L  
TPSFD/ TPHFD  
Full Delay (Legacy Delay or Default Delay)  
Global Clock Input and IFF(2) without MMCM  
XC6VLX75T  
1.33/  
0.03  
1.44/  
0.03  
1.75/  
0.03  
2.18/  
–0.22  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
XC6VLX130T  
XC6VLX195T  
XC6VLX240T  
XC6VLX365T  
XC6VLX550T  
XC6VLX760  
1.31/  
–0.08  
1.54/  
–0.08  
1.88/  
–0.08  
2.31/  
–0.12  
1.36/  
–0.11  
1.60/  
–0.11  
1.97/  
–0.11  
2.40/  
–0.25  
1.36/  
–0.11  
1.60/  
–0.11  
1.97/  
–0.11  
2.40/  
–0.25  
1.79/  
–0.28  
1.87/  
–0.28  
2.17/  
–0.28  
2.48/  
–0.24  
N/A  
2.22/  
–0.12  
2.36/  
–0.12  
2.77/  
–0.26  
N/A  
2.19/  
–0.24  
2.35/  
–0.24  
2.71/  
–0.21  
XC6VSX315T  
XC6VSX475T  
XC6VHX250T  
XC6VHX255T  
XC6VHX380T  
XC6VHX565T  
XQ6VLX130T  
XQ6VLX240T  
XQ6VLX550T  
XQ6VSX315T  
XQ6VSX475T  
1.75/  
–0.09  
1.85/  
–0.09  
2.06/  
–0.09  
2.47/  
–0.24  
N/A  
2.14/  
–0.14  
2.31/  
–0.14  
2.71/  
–0.30  
1.93/  
–0.22  
2.04/  
–0.22  
2.25/  
–0.22  
N/A  
N/A  
N/A  
N/A  
1.81/  
–0.33  
2.11/  
–0.33  
2.56/  
–0.33  
1.93/  
–0.11  
2.04/  
–0.11  
2.25/  
–0.11  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
2.20/  
–0.12  
2.39/  
–0.12  
1.54/  
–0.08  
1.88/  
–0.08  
2.31/  
–0.12  
1.60/  
–0.11  
1.97/  
–0.11  
2.40/  
–0.25  
N/A  
2.36/  
–0.12  
2.77/  
–0.26  
1.85/  
–0.09  
2.06/  
–0.09  
2.47/  
–0.24  
N/A  
2.31/  
2.71/  
–0.14  
–0.30  
Notes:  
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the  
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global  
Clock input signal using the fastest process, lowest temperature, and highest voltage.  
2. IFF = Input Flip-Flop or Latch  
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"  
is listed, there is no positive hold time.  
DS152 (v3.6) March 18, 2014  
www.xilinx.com  
Product Specification  
57  
 
 
 
 
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