Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 64: MMCM Specification (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
1.5
RSTMINPULSE
FPFDMAX
Minimum Reset Pulse Width
1.5
550
1.5
500
1.5
450
ns
Maximum Frequency at the Phase Frequency
450
MHz
Detector with Bandwidth Set to High or Optimized(9)
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
300
135
10
300
135
10
300
135
10
300
135
10
MHz
MHz
MHz
FPFDMIN
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
Minimum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
TFBDELAY
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
3 ns Max or one CLKIN cycle
TMMCMDCK_PSEN
TMMCMCKD_PSEN
/
1.04
0.00
1.04
0.00
1.04
0.00
1.04
0.00
ns
ns
ns
TMMCMDCK_PSINCDEC
TMMCMCKD_PSINCDEC
/
Setup and Hold of Phase Shift Increment/Decrement
Phase Shift Clock-to-Out of PSDONE
1.04
0.00
1.04
0.00
1.04
0.00
1.04
0.00
TMMCMCKO_PSDONE
0.32
0.34
0.38
0.38
Notes:
1. When DIVCLK_DIVIDE = 3 or 4, F
is 315 MHz.
INMAX
2. This duty cycle specification does not apply to the GTH_QUAD (GTH) to MMCM connection. The GTH transceivers drive the MMCMs at the
following maximum frequencies: 323 MHz for -1 speed grade devices, 350 MHz for -2 speed grade devices, or 350 MHz for -3 speed grade
devices.
3. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4. The static offset is measured between any MMCM outputs with identical phase.
5. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
6. Includes global clock buffer.
7. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
8. When CLKOUT4_CASCADE = TRUE, F
is 0.036 MHz.
OUTMIN
9. In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.
DS152 (v3.6) March 18, 2014
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Product Specification
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