Pinout Descriptions
TQ144: 144-lead Thin Quad Flat Package
The XC3S50A is available in the 144-lead thin quad flat
package, TQ144.
Table 66: Spartan-3A TQ144 Pinout(Continued)
Pin Name
IP_0/VREF_0
Bank
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Pin
P123
P119
P136
P79
P78
P76
P77
P75
P84
P82
P85
P83
P88
P87
P92
P90
P93
P91
P98
P96
P101
P99
P104
P102
P105
P103
P80
P97
P86
P95
P62
P38
P37
P41
P39
P44
P42
P45
P43
P48
Type
VREF
VCCO
VCCO
I/O
Table 66 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
VCCO_0
VCCO_0
IO_1
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1
DUAL
DUAL
DUAL
DUAL
I/O
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L03P_1
I/O
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
IO_L05N_1/TRDY1/RHCLK3
IO_L05P_1/RHCLK2
IO_L06N_1/RHCLK5
IO_L06P_1/RHCLK4
IO_L07N_1/RHCLK7
IO_L07P_1/IRDY1/RHCLK6
IO_L08N_1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
Pinout Table
Table 66: Spartan-3A TQ144 Pinout
Bank
0
Pin Name
Pin
Type
I/O
IO_0
P142
P111
P110
P113
P112
P117
P115
P116
P114
P121
P120
P126
P124
P127
P125
P131
P129
P132
P130
P135
P134
P139
P138
P143
P141
P140
0
IO_L01N_0
I/O
0
IO_L01P_0
I/O
0
IO_L02N_0
I/O
0
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
IO_L08P_1
I/O
0
IO_L09N_1
I/O
0
IO_L03P_0
I/O
IO_L09P_1
I/O
0
IO_L04N_0
I/O
IO_L10N_1
I/O
0
IO_L04P_0
I/O
IO_L10P_1
I/O
0
IO_L05N_0
I/O
IO_L11N_1
I/O
0
IO_L05P_0
I/O
IO_L11P_1
I/O
0
IO_L06N_0/GCLK5
IO_L06P_0/GCLK4
IO_L07N_0/GCLK7
IO_L07P_0/GCLK6
IO_L08N_0/GCLK9
IO_L08P_0/GCLK8
IO_L09N_0/GCLK11
IO_L09P_0/GCLK10
IO_L10N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IP_1/VREF_1
VREF
VREF
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
0
IP_1/VREF_1
0
VCCO_1
0
VCCO_1
0
IO_2/MOSI/CSI_B
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS1
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS2
IO_L05N_2/D7
0
0
0
0
0
IO_L10P_0
I/O
0
IO_L11N_0
I/O
0
IO_L11P_0
I/O
0
IO_L12N_0/PUDC_B
IO_L12P_0/VREF_0
IP_0
DUAL
VREF
INPUT
0
0
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
75
XILINX [ XILINX, INC ]
