Pinout Descriptions
User I/Os by Bank
Table 64 indicates how the 68 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Table 64: User I/Os Per Bank for the XC3S50A and XC3S200A in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
3
INPUT
DUAL
VREF
CLK
7
Top
0
1
2
3
15
13
26
14
68
1
0
0
1
2
1
0
3
1
1
1
6
Right
6
6
Bottom
Left
2
19
0
4
6
6
TOTAL
17
20
23
Footprint Migration Differences
The XC3S50A and XC3S200 have common VQ100 pinouts
except for some differences in alignment of differential I/O
pairs.
Differential I/O Alignment Differences
Some differential I/O pairs in the VQ100 on the XC3S50A
FPGA are aligned differently than the corresponding pairs
on the XC3S200A FPGAs, as shown in Table 65. All the
mismatched pairs are in I/O Bank 2. These differences are
indicated with the black diamond character () in the
footprint diagrams Figure 17 and Figure 18.
Table 65: Differential I/O Differences in VQ100
VQ100 Pin Bank
XC3S50A
IIO_L04P_2/VS2
IO_L03N_2/VS1
IO_L06P_2
XC3S200A
IO_L03N_2/VS2
IO_L04P_2/VS1
IO_L05N_2
P29
P30
P33
2
P34
IO_L05N_2/D7
IO_L06P_2/D7
IO_L11N_2/D0/DIN/ IO_L12P_2/D0/DIN/
P51
P52
MISO
MISO
IO_L12P_2/D1
IO_L11N_2/D1
72
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DS529-4 (v2.0) August 19, 2010
XILINX [ XILINX, INC ]
