Pinout Descriptions
VQ100 Footprint (XC3S50A)
Note pin 1 indicator in top-left corner and logo orientation.
TMS
TDI
1
2
3
4
5
6
7
8
9
75 TDO
74 GND
Bank 0
IO_L01P_3
IO_L01N_3
IO_L02P_3
73 IO_L06N_1
72 IO_L06P_1
71 IO_L05N_1
70 IO_L05P_1
IO_L02N_3
IP_3/VREF_3
69 GND
GND
68 IP_1/VREF_1
67 VCCO_1
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
VCCO_3 11
66 VCCINT
65 IO_L04N_1/RHCLK7
64 IO_L04P_1/IRDY1/RHCLK6
63 GND
IO_L04P_3/LHCLK2 12
IO_L04N_3/IRDY2/LHCLK3 13
GND 14
62 IO_L03N_1/TRDY1/RHCLK3
61 IO_L03P_1/RHCLK2
60 IO_L02N_1/RHCLK1
59 IO_L02P_1/RHCLK0
58 GND
IO_L05P_3/TRDY2/LHCLK6 15
IO_L05N_3/LHCLK7 16
VCCINT 17
GND 18
IO_L06P_3 19
57 IO_L01N_1
IO_L06N_3 20
56 IO_L01P_1
IP_3 21
55 VCCAUX
VCCAUX 22
54 DONE
IO_L01P_2/M1 23
IO_L02P_2/M2 24
IO_L01N_2/M0 25
53 IO_L12N_2/CCLK
52 IO_L12P_2/D1(◆)
51 IO_L11N_2/D0/DIN/MISO (◆)
Bank 2
Figure 17: VQ100 Package Footprint - XC3S50A (Top View)
I/O: Unrestricted, general-purpose
DUAL: Configuration pins, then
VREF: User I/O or input voltage
17
20
23
6
6
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
2
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
2
0
4
4
3
pins
voltage (+1.2V)
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
13
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
73
XILINX [ XILINX, INC ]
