Pinout Descriptions
User I/Os by Bank
Table 67 indicates how the 108 available user-I/O pins are
distributed between the four I/O banks on the TQ144
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3S50A in the TQ144 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
14
11
2
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
27
25
1
0
0
1
2
1
4
3
2
1
2
8
Right
8
Bottom
Left
30
21
0
6
26
15
42
8
TOTAL
108
26
30
Footprint Migration Differences
The XC3S50A FPGA is the only Spartan-3A device offered
in the TQ144 package.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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