Pinout Descriptions
VQ100: 100-lead Very Thin Quad Flat Package
The XC3S50A and XC3S200 are available in the 100-lead
very thin quad flat package, VQ100.
Table 63: Spartan-3A VQ100 Pinout(Continued)
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
IO_L02P_1/RHCLK0
IO_L03N_1/TRDY1/RHCLK3
IO_L03P_1/RHCLK2
IO_L04N_1/RHCLK7
IO_L04P_1/IRDY1/RHCLK6
IO_L05N_1
P59
P62
P61
P65
P64
P71
P70
P73
P72
P68
P67
P46
P25
P23
P27
P24
CLK
CLK
CLK
CLK
CLK
IO
Table 63 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
The VQ100 does not support Suspend mode (SUSPEND
and AWAKE are not connected), the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode,
or daisy chain configuration (DOUT is not connected).
IO_L05P_1
IO
IO_L06N_1
IO
IO_L06P_1
IO
Table 63 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A, highlighted in light blue. See "Footprint
Migration Differences," page 72 for additional information.
IP_1/VREF_1
VREF
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
VCCO_1
IO_2/MOSI/CSI_B
IO_L01N_2/M0
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L03N_2/VS1 (3S50A)
IO_L04P_2/VS1 (3S200A)
2
P30
DUAL
Pinout Table
2
2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
P28
P31
DUAL
DUAL
Table 63: Spartan-3A VQ100 Pinout
Bank
0
Pin Name
IO_0/GCLK11
Pin
P90
P78
P77
P84
P83
P86
P85
P89
P88
P94
P93
P99
P98
P97
P82
P79
P96
P57
P56
P60
Type
CLK
IO
IO_L04P_2/VS2 (3S50A)
IO_L03N_2/VS2 (3S200A)
2
2
P29
P34
DUAL
DUAL
0
IO_L01N_0
IO_L05N_2/D7 (3S50A)
IO_L06P_2/D7 (3S200A)
0
IO_L01P_0/VREF_0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L04N_0/GCLK9
IO_L04P_0/GCLK8
IO_L05N_0
VREF
CLK
CLK
CLK
CLK
CLK
CLK
IO
0
2
2
IO_L05P_2
P32
P35
IO
0
IO_L06N_2/D6
DUAL
0
IO_L06P_2 (3S50A)
IO_L05N_2 (3S200A)
2
P33
IO
0
2
2
2
2
2
2
2
2
IO_L07N_2/D4
P37
P36
P41
P40
P44
P43
P49
P48
DUAL
DUAL
CLK
0
IO_L07P_2/D5
0
IO_L08N_2/GCLK15
IO_L08P_2/GCLK14
IO_L09N_2/GCLK1
IO_L09P_2/GCLK0
IO_L10N_2/D3
0
CLK
0
IO_L05P_0
IO
CLK
0
IO_L06N_0/PUDC_B
IO_L06P_0/VREF_0
IP_0
DUAL
VREF
IP
CLK
0
DUAL
DUAL
0
IO_L10P_2/INIT_B
0
IP_0/VREF_0
VREF
VCCO
VCCO
IO
IO_L11N_2/D0/DIN/MISO
(3S50A)
IO_L12P_2/D0/DIN/MISO
(3S200A)
0
VCCO_0
2
P51
DUAL
0
VCCO_0
1
IO_L01N_1
2
2
IO_L11P_2/D2
P50
P53
DUAL
DUAL
1
IO_L01P_1
IO
IO_L12N_2/CCLK
1
IO_L02N_1/RHCLK1
CLK
70
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
XILINX [ XILINX, INC ]
