Spartan-3E FPGA Family: Functional Description
Description
Table 10: Slice Inputs and Outputs (Cont’d)
Name
Location
SLICEM Bottom
SLICEL/M Bottom
SLICEL/M Top
Direction
Output
Input
SHIFTOUT
Shift data output from F-LUT RAM
CIN
COUT
X
Carry chain input
Output
Output
Output
Output
Output
Output
Output
Carry chain output
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output
Y
Combinatorial output
XB
YB
XQ
YQ
SLICEL/M Bottom
SLICEL/M Top
Combinatorial output from carry or F-LUT SRL16 (SLICEM)
Combinatorial output from carry or G-LUT SRL16 (SLICEM)
SLICEL/M Bottom
SLICEL/M Top
FFX output
FFY output
2. Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
Main Logic Paths
Central to the operation of each slice are two nearly
3. Control the wide function multiplexer F5MUX (or
identical data paths at the top and bottom of the slice. The
description that follows uses names associated with the
bottom path. (The top path names appear in parentheses.)
The basic path originates at an interconnect switch matrix
outside the CLB. See Interconnect for more information on
the switch matrix and the routing connections.
FiMUX).
4. Via multiplexers, serve as an input to the carry chain.
5. Drive the DI input of the LUT.
6. BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
‘F’ (or ‘G’) that performs logic operations. The LUT Data
output, ‘D’, offers five possible paths:
7. Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
The control inputs CLK, CE, SR, BX and BY have
programmable polarity. The LUT inputs do not need
programmable polarity because their function can be
inverted inside the LUT.
1. Exit the slice via line “X” (or “Y”) and return to
interconnect.
The sections that follow provide more detail on individual
functions of the slice.
2. Inside the slice, “X” (or “Y”) serves as an input to the
DXMUX (or DYMUX) which feeds the data input, “D”, of
the FFX (or FFY) storage element. The “Q” output of the
storage element drives the line XQ (or YQ) which exits
the slice.
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function
generator and is the main resource for implementing logic
functions. Furthermore, the LUTs in each SLICEM pair can
be configured as Distributed RAM or a 16-bit shift register,
as described later.
3. Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on “X” (or “Y”).
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by
cascading LUTs or by using the wide function multiplexers
that are described later.
5. Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The “D” outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
BY in the top half) can take any of several possible
branches:
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB
output or to the CLB storage element. See Figure 18.
1. Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
DS312 (v4.2) December 14, 2018
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