欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC3S500E-4FTG256CS1 参数 Datasheet PDF下载

XC3S500E-4FTG256CS1图片预览
型号: XC3S500E-4FTG256CS1
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA256,]
分类和应用: 时钟可编程逻辑
文件页数/大小: 227 页 / 6528 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第6页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第7页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第8页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第9页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第11页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第12页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第13页浏览型号XC3S500E-4FTG256CS1的Datasheet PDF文件第14页  
Spartan-3E FPGA Family: Functional Description  
pair of storage elements to the IQ1 and IQ2 lines. The  
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal  
logic. The delay element can be set to ensure a hold  
time of zero (see Input Delay Functions).  
Introduction  
As described in Architectural Overview, the Spartan-3E  
FPGA architecture consists of five fundamental functional  
elements:  
The output path, starting with the O1 and O2 lines,  
carries data from the FPGA’s internal logic through a  
multiplexer and then a three-state driver to the IOB  
pad. In addition to this direct path, the multiplexer  
provides the option to insert a pair of storage elements.  
Input/Output Blocks (IOBs)  
Configurable Logic Block (CLB) and Slice Resources  
Block RAM  
Dedicated Multipliers  
The 3-state path determines when the output driver is  
high impedance. The T1 and T2 lines carry data from  
the FPGA’s internal logic through a multiplexer to the  
output driver. In addition to this direct path, the  
multiplexer provides the option to insert a pair of  
storage elements.  
Digital Clock Managers (DCMs)  
The following sections provide detailed information on each  
of these functions. In addition, this section also describes  
the following functions:  
Clocking Infrastructure  
Interconnect  
All signal paths entering the IOB, including those  
associated with the storage elements, have an inverter  
option. Any inverter placed on these paths is  
automatically absorbed into the IOB.  
Configuration  
Powering Spartan-3E FPGAs  
Input/Output Blocks (IOBs)  
For additional information, refer to the “Using I/O  
Resources” chapter in UG331.  
IOB Overview  
The Input/Output Block (IOB) provides a programmable,  
unidirectional or bidirectional interface between a package  
pin and the FPGA’s internal logic. The IOB is similar to that  
of the Spartan-3 family with the following differences:  
Input-only blocks are added  
Programmable input delays are added to all blocks  
DDR flip-flops can be shared between adjacent IOBs  
The unidirectional input-only block has a subset of the full  
IOB capabilities. Thus there are no connections or logic for  
an output path. The following paragraphs assume that any  
reference to output functionality does not apply to the  
input-only blocks. The number of input-only blocks varies  
with device size, but is never more than 25% of the total IOB  
count.  
Figure 5 is a simplified diagram of the IOB’s internal  
structure. There are three main signal paths within the IOB:  
the output path, input path, and 3-state path. Each path has  
its own pair of storage elements that can act as either  
registers or latches. For more information, see Storage  
Element Functions. The three main signal paths are as  
follows:  
The input path carries data from the pad, which is  
bonded to a package pin, through an optional  
programmable delay element directly to the I line. After  
the delay element, there are alternate routes through a  
DS312 (v4.2) December 14, 2018  
www.xilinx.com  
Product Specification  
10