Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 5
T
TFF1
D
T1
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
V
CCO
OFF1
D
O1
Q
CE
CK
OTCLK1
Pull-Up
ESD
ESD
SR REV
DDR
MUX
I/O
Pin
OCE
O2
Program-
mable
Output
Driver
Pull-
Down
Q
D
OFF2
CE
CK
OTCLK2
SR REV
Keeper
Latch
Output Path
Programmable
Delay
I
LVCMOS, LVTTL, PCI
IQ1
Programmable
Delay
Single-ended Standards
using V
REF
D
IDDRIN1
IDDRIN2
Q
V
REF
IFF1
CE
CK
Pin
ICLK1
ICE
SR REV
Differential Standards
I/O Pin
from
Adjacent
IOB
IQ2
D
Q
IFF2
CE
ICLK2
CK
SR REV
SR
REV
Input Path
DS312-2_19_110606
Figure 5: Simplified IOB Diagram
DS312 (v4.2) December 14, 2018
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Product Specification
11
XILINX [ XILINX, INC ]
