R
Pinout Descriptions
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
FG320: 320-ball Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in Table 24 and Figure 8.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FG320 package.
Table 24 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in Table 24 and with the
black diamond character (ꢃ) in both Table 24 and in
Figure 8.
Pinout Table
Table 24: FG320 Package Pinout
FG320
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
Ball
Type
0
IP
IO
IO
A7
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
0
IO
IO
IO
IP
IO
IO
IO
IO
IO
IO
IO
IO
A8
A11
C4
I/O
I/O
I/O
D13
500E: INPUT
1200E: I/O
1600E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
E13
G9
I/O
I/O
IO/VREF_0
IO/VREF_0
IO/VREF_0
B11
A16
B16
C14
D14
A14
B14
B13
A13
E12
F12
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
IO_L06P_0
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
39
Advance Product Specification
XILINX [ XILINX, INC ]
