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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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R
Pinout Descriptions  
and the XC3S1200E. The arrows indicate the direction for  
easy migration. A double-ended arrow (ꢁꢂ) indicates that  
the two pins have identical functionality. A left-facing arrow  
() indicates that the pin on the device on the right uncon-  
ditionally migrates to the pin on the device on the left. It may  
be possible to migrate the opposite direction depending on  
the I/O configuration. For example, an I/O pin (Type = I/O)  
can migrate to an input-only pin (Type = INPUT) if the I/O  
pin is configured as an input.  
Footprint Migration Differences  
Table 23 summarizes any footprint and functionality differ-  
ences between the XC3S250E, the XC3S500E, and the  
XC3S1200E FPGAs that may affect easy migration  
between devices in the FG256 package. There are 26 such  
balls. All other pins not listed in Table 23 unconditionally  
migrate between Spartan-3E devices available in the FT256  
package.  
The XC3S250E is duplicated on both the left and right sides  
of the table to show migrations to and from the XC3S500E  
Table 23: FT256 Footprint Migration Differences  
FT256  
Ball  
XC3S250E  
Type  
XC3S500E  
Type  
XC3S1200E  
Type  
XC3S250E  
Type  
Bank  
0
Migration  
ꢁꢂ  
Migration  
Migration  
B6  
B7  
INPUT  
N.C.  
INPUT  
I/O  
INPUT  
N.C.  
0
I/O  
ꢁꢂ  
I/O  
B10  
C7  
0
INPUT  
N.C.  
ꢁꢂ  
INPUT  
I/O  
I/O  
INPUT  
N.C.  
0
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
I/O  
D16  
E13  
E16  
F3  
1
VREF(I/O)  
N.C.  
VREF(INPUT)  
I/O  
VREF(INPUT)  
VREF(I/O)  
N.C.  
1
I/O  
1
N.C.  
I/O  
I/O  
N.C.  
3
N.C.  
I/O  
I/O  
N.C.  
F4  
3
N.C.  
VREF  
I/O  
VREF  
INPUT  
VREF  
I/O  
N.C.  
F5  
3
I/O  
ꢁꢂ  
I/O  
L2  
3
N.C.  
VREF  
I/O  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
N.C.  
L3  
3
N.C.  
N.C.  
L4  
3
N.C.  
I/O  
I/O  
N.C.  
L12  
L13  
M4  
M7  
M14  
N2  
1
N.C.  
I/O  
I/O  
N.C.  
1
N.C.  
I/O  
I/O  
N.C.  
3
N.C.  
I/O  
I/O  
N.C.  
2
INPUT  
I/O  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
INPUT  
I/O  
I/O  
INPUT  
I/O  
1
INPUT  
VREF(INPUT)  
I/O  
3
VREF(I/O)  
N.C.  
VREF(I/O)  
I/O  
VREF(I/O)  
N.C.  
N7  
2
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
ꢁꢂ  
N14  
N15  
P7  
1
N.C.  
I/O  
I/O  
N.C.  
1
N.C.  
VREF  
I/O  
VREF  
I/O  
N.C.  
2
N.C.  
N.C.  
P10  
R10  
T12  
2
N.C.  
I/O  
I/O  
N.C.  
2
N.C.  
VREF  
INPUT  
VREF  
I/O  
N.C.  
2
INPUT  
ꢁꢂ  
19  
INPUT  
DIFFERENCES  
7
26  
Legend:  
This pin is identical on both the device on the left and the right.  
ꢁꢂ  
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible  
depending on how the pin is configured for the device on the right.  
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible  
depending on how the pin is configured for the device on the left.  
DS312-4 (v1.1) March 21, 2005  
www.xilinx.com  
37  
Advance Product Specification  
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