R
Pinout Descriptions
FT256 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
L17N_0
VREF_0
INPUT
L10P_0
GCLK8
I/O
L09N_0
GCLK7
I/O
L09P_0
GCLK6
I/O
L03N_0
VREF_0
I/O
L17P_0
I/O
L01N_0
VCCAUX
VCCAUX
GND
TDI
INPUT
I/O
I/O
TCK
GND
A
B
C
D
E
F
I/O
L13P_0
I/O
L19N_0
HSWAP
INPUT
L10N_0
GCLK9
I/O
L05N_0
VREF_0
INPUT
ꢁꢂ
INPUT
ꢁꢂ
I/O
L01P_3
I/O
L01N_3
I/O
L03P_0
I/O
L01P_0
VCCO_0
VCCO_0
I/O
GND
TMS
INPUT
ꢃ
I/O
L13N_0
I/O
L02N_3
VREF_3
I/O
L11P_0
GCLK10
I/O
L19N_1
LDC2
I/O
L19P_1
LDC1
I/O
L02P_3
I/O
L19P_0
I/O
L18N_0
I/O
L18P_0
I/O
L15P_0
INPUT INPUT
I/O
L05P_0
INPUT
L02N_0
INPUT
TDO
L07N_0
L07P_0
ꢃ
INPUT
VREF_1
I/O
L14N_0
VREF_0 GCLK11
I/O
L11N_0
I/O
L18N_1
LDC0
I/O
L18P_1
HDC
I/O
L05P_3
INPUT
L16P_0
I/O
L15N_0
I/O
VREF_0
I/O
L06P_0
I/O
L04P_0
INPUT
L02P_0
PROG_B
INPUT
VCCINT
VCCINT
ꢁꢂ
I/O
L17P_1
I/O
L17N_1
I/O
L08P_0
GCLK4
I/O
L05N_3
I/O
L03P_3
I/O
L03N_3
INPUT
L16N_0
I/O
L14P_0
I/O
L12P_0
I/O
L06N_0
I/O
L04N_0
VCCO_3
VCCO_1
VCCINT
VCCINT
INPUT
ꢃ
ꢃ
I/O
L04N_3
VREF_3
ꢃ
I/O
L04P_3
I/O
L08N_0
GCLK5
INPUT
ꢁꢂ
I/O
L12N_0
I/O
L16N_1
I/O
L16P_1
I/O
L15P_1
I/O
L15N_1
VCCAUX
VCCO_0
GND
VCCO_0
GND
VCCAUX
INPUT
I/O
GND
GND
ꢃ
I/O
L14N_1
A0
I/O
L13P_1
A2
I/O
L13N_1
A1
INPUT
VREF_3 L07N_3
I/O
L07P_3
I/O
L06N_3
I/O
L06P_3
I/O
L14P_1
VCCO_3
VCCO_1
GND
GND
GND
GND
GND
GND
GND
INPUT
I/O
L12P_1
A4
G
H
J
I/O
L11P_1
A6
I/O
L09N_3
LHCLK3
IRDY2
I/O
I/O
I/O
L09P_3
LHCLK2
I/O
L08P_3
I/O
L08N_3
LHCLK0 LHCLK1
INPUT
VREF_1
L12N_1
A3
L11N_1
A5
INPUT
GND
I/O
L10P_3
LHCLK4
TRDY2
GND
GND
INPUT
I/O
L09N_1
A9
RHCLK1
RHCLK4
IRDY1
RHCLK7 RHCLK6
RHCLK5
I/O
I/O
I/O
L10N_3
I/O
L11N_3
I/O
L11P_3
L10N_1
I/O
L12P_3
L10P_1
A8
INPUT
VCCO_3
GND
GND
GND
INPUT INPUT
GND
A7
RHCLK3
LHCLK5 LHCLK7 LHCLK6
RHCLK2
TRDY1
I/O
I/O
I/O
L07P_1
A12
I/O
L08N_1
VREF_1
I/O
L12N_3
I/O
L13P_3
I/O
L13N_3
I/O
L15P_3
I/O
L08P_1
L09P_1
A10
VCCO_1
L07N_1
INPUT
GND
GND
I/O
L09N_2
D6
GCLK13
GND
K
L
A11
RHCLK0
I/O
L14N_3
VREF_3
ꢃ
I/O
L14P_3
I/O
L17N_3
I/O
L05P_1
I/O
L05N_1
I/O
L13P_2
M0
I/O
L15N_3
I/O
L06P_1
I/O
L06N_1
VCCAUX
VCCO_2
VCCO_2
VCCAUX
GND
ꢃ
ꢃ
ꢃ
ꢃ
I/O
I/O
I/O
I/O
L04N_1
VREF_1
INPUT
ꢁꢂ
INPUT
ꢁꢂ
I/O
L16P_3
I/O
L05P_2
I/O
L15N_2
INPUT
L17N_2
L09P_2
D7
L13N_2
DIN
VCCO_3
VCCO_1
INPUT L17P_3 VCCINT
VCCINT INPUT
M
N
P
R
T
ꢃ
GCLK12
D0
I/O
INPUT
VREF_3
I/O
L07P_2
I/O
L03P_1
I/O
I/O
I/O
I/O
L18N_2
A20
I/O
L16N_3
I/O
L05N_2
I/O
L15P_2
INPUT
L17P_2
I/O
L04P_1
L03N_1
VREF_1
L03N_2
L10P_2
D4
L12N_2
D1
INPUT VCCINT
VCCINT
MOSI
CSI_B
ꢁꢂ
ꢃ
ꢃ
GCLK14
GCLK3
ꢃ
I/O
L07N_2
I/O
L14P_2
I/O
L03P_2
DOUT
BUSY
I/O
I/O
I/O
I/O
L01P_2
I/O
L01N_2
I/O
L16N_2
A22
I/O
L18P_2
A21
I/O
L02N_1
A13
I/O
L02P_1
A14
I/O
L18N_3
I/O
L18P_3
I/O
L06N_2
I/O
VREF_2
L10N_2
D3
L12P_2
D2
L20P_2
VS0
CSO_B
INIT_B
ꢃ
ꢃ
GCLK15
GCLK2
A17
I/O
L14N_2
VREF_2
ꢃ
INPUT
I/O
I/O
L16P_2
A23
I/O
L20N_2
CCLK
I/O
L01N_1
A15
I/O
L01P_1
A16
I/O
L19N_3
I/O
L19P_3
INPUT
I/O
I/O
L06P_2
INPUT
L08P_2
L11N_2
M2
L19N_2
VS1
VCCO_2
VCCO_2
GND
L02N_2 VREF_2
GCLK1
A18
INPUT
L11P_2
RDWR_B
GCLK0
I/O
INPUT
L08N_2
VREF_2
INPUT
ꢁꢂ
INPUT
L02P_2
I/O
L04P_2
I/O
L04N_2
I/O
D5
I/O
M1
L19P_2
VS2
VCCAUX
VCCAUX
GND
INPUT
INPUT DONE
GND
A19
Bank 2
DS312-4_05_021705
Figure 7: FT256 Package Footprint (top view)
JTAG: Dedicated JTAG port
CONFIG: Dedicated
configuration pins
VCCINT: Internal core supply
voltage (+1.2V)
2
4
8
pins
GND: Ground
VCCO: Output voltage supply
for bank
VCCAUX: Auxiliary supply
voltage (+2.5V)
28
16
8
Migration Difference: For
flexible package migration,
use these pins as inputs.
Unconnected pins on
XC3S250E
6
18
ꢁꢂ
ꢃ
38
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification