R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
P72
Type
CONFIG
CONFIG
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
DONE
DONE
PROG_B
TCK
PROG_B
TCK
P1
P110
P144
P109
P108
P30
TDI
TDI
JTAG
TDO
TDO
JTAG
TMS
TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
P65
P102
P137
P9
P45
P80
P115
User I/Os by Bank
Table 13 and Table 14 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
0
Right
0
21
20
0
Bottom
Left
26
0
4
0
28
13
22
4
8
TOTAL
108
19
42
16
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
26
28
6
5
2
2
2
3
9
8
0
Right
0
21
20
0
Bottom
Left
26
0
4
0
28
11
20
6
8
TOTAL
108
21
42
16
18
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
