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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Pinout Descriptions  
The arrows indicate the direction for easy migration. For  
example, a left-facing arrow indicates that the pin on the  
XC3S250E unconditionally migrates to the pin on the  
XC3S100E. It may be possible to migrate the opposite  
direction depending on the I/O configuration. For example,  
an I/O pin (Type = I/O) can migrate to an input-only pin  
(Type = INPUT) if the I/O pin is configured as an input.  
Footprint Migration Differences  
Table 15 summarizes any footprint and functionality differ-  
ences between the XC3S100E and the XC3S250E FPGAs  
that may affect easy migration between devices. There are  
four such pins. All other pins not listed in Table 15 uncondi-  
tionally migrate between Spartan-3E devices available in  
the TQ144 package.  
Table 15: TQ144 Footprint Migration Differences  
TQ144 Pin  
P10  
Bank  
XC3S100E Type  
Migration  
XC3S250E Type  
INPUT  
3
3
3
2
I/O  
I/O  
4
P29  
INPUT  
P31  
VREF(INPUT)  
VREF(INPUT)  
VREF(I/O)  
VREF(I/O)  
P66  
DIFFERENCES  
Legend:  
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be  
possible depending on how the pin is configured for the device on the right.  
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be  
possible depending on how the pin is configured for the device on the left.  
The pinout changed slightly between the XC3S100E engi-  
neering samples and the production devices, as shown in  
Table 16. In the engineering samples, the mode select pins  
M1 and M0 overlap with two global clock inputs feeding the  
bottom edge global buffers and DCMs. In the production  
devices, the mode pins are swapped with parallel mode  
data pins, D1 and D2. This way, these two mode pins do not  
interfere with global clock inputs.  
Table 16: XC3S100E Pinout Changes between  
Production Devices and Engineering Samples  
XC3S100E  
Production  
Devices  
XC3S100E  
Engineering  
Samples  
TQ144 Pin  
P58  
D2/GCLK2  
D1/GCLK3  
M1  
M1/GCLK2  
M0/GCLK3  
D2  
P59  
P60  
P62  
M0  
D1  
DS312-4 (v1.1) March 21, 2005  
www.xilinx.com  
19  
Advance Product Specification  
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