— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
R
Virtex-II Platform FPGAs: Functional Description
devices, some V
pins used in larger devices do not con-
CCO
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
Bank 0
Bank 1
connected to V
to permit migration to a larger device.
CCO
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:
1. Combining output standards only. Output standards
with the same output V
requirement can be
CCO
combined in the same bank.
Compatible example:
Bank 5
Bank 4
SSTL2_I and LVDS_25_DCI outputs
Incompatible example:
ug002_c2_014_112900
SSTL2_I (output VCCO = 2.5V) and
LVCMOS33 (output VCCO = 3.3V) outputs
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS/CSG, FG/FGG, & BG/BGG)
2. Combining input standards only. Input standards
with the same input V
can be combined in the same bank.
Compatible example:
and input V
requirements
CCO
REF
Some input standards require a user-supplied threshold
voltage (V
), and certain user-I/O pins are automatically
REF
configured as V
inputs. Approximately one in six of the
REF
LVCMOS15 and HSTL_IV inputs
I/O pins in the bank assume this role.
Incompatible example:
LVCMOS15 (input VCCO = 1.5V) and
LVCMOS18 (input VCCO = 1.8V) inputs
Incompatible example:
Bank 1
Bank 0
HSTL_I_DCI_18 (VREF = 0.9V) and
HSTL_IV_DCI_18 (VREF = 1.1V) inputs
3. Combining input standards and output standards.
Input standards and output standards with the same
input V
and output V
requirement can be
CCO
CCO
combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
Bank 4
Bank 5
LVDS_25 output (output VCCO = 2.5V) and
HSTL_I_DCI_18 input (input VCCO = 1.8V)
ds031_66_112900
4. Combining bi-directional standards with input or
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
V
pins within a bank are interconnected internally, and
REF
5. Additional rules for combining DCI I/O standards.
consequently only one V
voltage can be used within
REF
each bank. However, for correct operation, all V
the bank must be connected to the external reference volt-
age source.
pins in
a. No more than one Single Termination type (input or
output) is allowed in the same bank.
REF
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
The V
and the V
pins for each bank appear in the
REF
CCO
b. No more than one Split Termination type (input or
output) is allowed in the same bank.
device pinout tables. Within a given package, the number of
and V pins can vary depending on the size of
V
REF
CCO
device. In larger devices, more I/O pins convert to V
Incompatible example:
REF
HSTL_I_DCI input and HSTL_II_DCI input
pins. Since these are always a superset of the V
pins
REF
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
The implementation tools will enforce these design rules.
Table 5 summarizes all standards and voltage supplies.
All V
pins for the largest device anticipated must be con-
REF
nected to the V
voltage and not used for I/O. In smaller
REF
DS031-2 (v4.0) April 7, 2014
Product Specification
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