— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
R
Virtex-II Platform FPGAs: Functional Description
Logic Resources
Table 2: Supported Differential Signal I/O Standards
IOB blocks include six storage elements, as shown in
Figure 2.
Output Input Input
Output
VOD
I/O Standard
VCCO
VCCO
N/R(1)
N/R
VREF
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
LVPECL_33
3.3
0.490 - 1.220
0.500 - 0.700
0.250 - 0.400
0.250 - 0.400
0.440 - 0.820
0.440 - 0.820
0.250 - 0.450
0.500 - 0.700
LDT_25
2.5
IOB
LVDS_33
3.3
N/R
Input
DDR mux
LVDS_25
2.5
N/R
Reg
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
3.3
N/R
OCK1
Reg
2.5
N/R
ICK1
2.5
N/R
Reg
2.5
N/R
3-State
OCK2
Reg
Notes:
1. N/R = no requirement.
ICK2
DDR mux
Table 3: Supported DCI I/O Standards
Reg
I/O
Output Input Input Termination
OCK1
Standard
VCCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
VCCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
VREF
N/R(4)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
Type
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Split
PAD
LVDCI_33(1)
Reg
LVDCI_DV2_33(1)
LVDCI_25(1)
Output
OCK2
LVDCI_DV2_25(1)
LVDCI_18(1)
DS031_29_100900
LVDCI_DV2_18(1)
LVDCI_15(1)
Figure 2: Virtex-II IOB Block
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
LVDCI_DV2_15(1)
GTL_DCI
GTLP_DCI
1.0
HSTL_I_DCI
0.75
0.75
0.9
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
HSTL_II_DCI
Split
HSTL_III_DCI
Single
Single
Split
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI(3)
SSTL18_II_DCI
SSTL2_I_DCI(2)
SSTL2_II_DCI(2)
SSTL3_I_DCI(2)
SSTL3_II_DCI(2)
LVDS_25_DCI
LVDSEXT_25_DCI
0.9
0.9
0.9
Split
1.1
Single
Single
Split
1.1
0.9
0.9
Split
1.25
1.25
1.5
Split
Split
Split
1.5
Split
N/R
N/R
Split
Split
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half of
the reference resistors.
2. These are SSTL compatible.
3. SSTL18_I is not a JEDEC-supported standard.
4. N/R = no requirement.
DS031-2 (v4.0) April 7, 2014
Product Specification
www.xilinx.com
Module 2 of 4
2
XILINX [ XILINX, INC ]
