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XC2V2000-4BGG575I 参数 Datasheet PDF下载

XC2V2000-4BGG575I图片预览
型号: XC2V2000-4BGG575I
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2688 CLBs, 2000000 Gates, 650MHz, 24192-Cell, CMOS, PBGA575, 31 X 31 MM, 1.27 MM PITCH, LEAD FREE, MS-034BAN-1, BGA-575]
分类和应用: 时钟可编程逻辑
文件页数/大小: 319 页 / 1869 K
品牌: XILINX [ XILINX, INC ]
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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —  
R
Virtex-II Platform FPGAs: Functional Description  
DCM  
180° 0°  
FDDR  
FDDR  
D1  
D1  
Q1  
CLK1  
Q1  
CLK1  
CLOCK  
Q
Q
DDR MUX  
DDR MUX  
D2  
D2  
Q2  
CLK2  
Q2  
CLK2  
(50/50 duty cycle clock)  
DS031_26_100900  
Figure 3: Double Data Rate Registers  
The DDR mechanism shown in Figure 3 can be used to mir-  
ror a copy of the clock on the output. This is useful for prop-  
agating a clock along the data that has an identical delay. It  
is also useful for multiple clock generation, where there is a  
unique clock driver for every clock load. Virtex-II devices  
can produce many copies of a clock with very little skew.  
For each storage element, the SRHIGH, SRLOW, INIT0,  
and INIT1 attributes are independent. Synchronous or  
asynchronous set / reset is consistent in an IOB block.  
All the control signals have independent polarity. Any  
inverter placed on a control input is automatically absorbed.  
Each register or latch (independent of all other registers or  
latches) (see Figure 4) can be configured as follows:  
Each group of two registers has a clock enable signal (ICE  
for the input registers, OCE for the output registers, and  
TCE for the 3-state registers). The clock enable signals are  
active High by default. If left unconnected, the clock enable  
for that storage element defaults to the active state.  
No set or reset  
Synchronous set  
Synchronous reset  
Synchronous set and reset  
Asynchronous set (preset)  
Asynchronous reset (clear)  
Asynchronous set and reset (preset and clear)  
Each IOB block has common synchronous or asynchronous  
set and reset (SR and REV signals).  
SR forces the storage element into the state specified by the  
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.  
SRLOW forces a logic “0”. When SR is used, a second input  
(REV) forces the storage element into the opposite state. The  
reset condition predominates over the set condition. The ini-  
tial state after configuration or global initialization state is  
defined by a separate INIT0 and INIT1 attribute. By default,  
the SRLOW attribute forces INIT0, and the SRHIGH attribute  
forces INIT1.  
The synchronous reset overrides a set, and an asynchro-  
nous clear overrides a preset.  
DS031-2 (v4.0) April 7, 2014  
Product Specification  
www.xilinx.com  
Module 2 of 4  
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