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R
Virtex-II Platform FPGAs: Functional Description
Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards (Continued)
Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards
VCCO
VREF
Input
1.1
Termination Type
VCCO
VREF
Input
N/R(1)
N/R
N/R
1.5
Termination Type
I/O Standard
HSTL_III_18
HSTL_IV_18
HSTL_I_18
HSTL_II_18
SSTL18_I
Output Input
Output
N/R
Input
N/R
I/O Standard
LVDS_33
Output Input
Output
N/R
Input
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Split
1.1
N/R
N/R
LVDSEXT_33
LVPECL_33
SSTL3_I
N/R
0.9
N/R
N/R
N/R
N/R
N/R
0.9
N/R
N/R
N/R
0.9
N/R
N/R
SSTL3_II
1.5
N/R
SSTL18_II
0.9
N/R
N/R
AGP
1.32
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.5
N/R
LVCMOS18
LVDCI_18
N/R
N/R
N/R
1.1
N/R
N/R
LVTTL
N/R
1.8
Series
Series
N/R
N/R
LVCMOS33
LVDCI_33
LVDCI_DV2_33
PCI33_3
3.3
N/R
LVDCI_DV2_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
HSTL_I_DCI_18
HSTL_II_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
HSTL_III
N/R
Series
Series
N/R
Single
Single
Split
Split
Split
Split
N/R
1.8
1.1
Single
N/R
3.3
0.9
PCI66_3
N/R
0.9
Split
N/R
PCIX
N/R
0.9
SSTL3_I_DCI
SSTL3_II_DCI
LVDS_25
N/R
0.9
Split
N/R
1.5
Split
N/R
0.9
N/R
N/R
N/R
N/R
N/R
1.25
1.25
N/R
N/R
N/R
N/R
HSTL_IV
0.9
N/R
N/R
LVDSEXT_25
LDT_25
N/R
N/R
HSTL_I
0.75
0.75
N/R
N/R
N/R
1
N/R
N/R
N/R
HSTL_II
N/R
N/R
ULVDS_25
BLVDS_25
SSTL2_I
N/R
N/R
LVCMOS15
LVDCI_15
N/R
N/R
N/R
Series
Series
Single
N/R
N/R
N/R
1.5
LVDCI_DV2_15
GTLP_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
GTL_DCI
N/R
SSTL2_II
N/R
2.5
Single
Single
Single
Split
Split
Single
N/R
LVCMOS25
LVDCI_25
LVDCI_DV2_25
LVDS_25_DCI
N/R
1.5
0.9
Series
Series
N/R
0.9
Single
N/R
0.75
0.75
0.8
2.5
Split
Single
N/R
LVDSEXT_25_DC
I
N/R
N/R
Split
1.2
1.2
SSTL2_I_DCI
SSTL2_II_DCI
1.25
1.25
N/R
Split
Split
GTLP
1
N/R
N/R
Split
GTL
0.8
N/R
N/R
Notes:
1. N/R = no requirement.
DS031-2 (v4.0) April 7, 2014
Product Specification
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