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XC2V1000-4FG456C 参数 Datasheet PDF下载

XC2V1000-4FG456C图片预览
型号: XC2V1000-4FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用: 可编程逻辑时钟
文件页数/大小: 311 页 / 1765 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex™-II Platform FPGAs: DC and Switching Characteristics  
Clock Distribution Switching Characteristics  
Table 19: Clock Distribution Switching Characteristics  
Speed Grade  
Description  
Symbol  
6  
5  
4  
Units  
0.47  
0.52  
0.59  
Global Clock Buffer I input to O output  
T
ns, Max  
GIO  
CLB Switching Characteristics  
Delays originating at F/G inputs vary slightly according to the input used (see Figure 16 in Module 2). The values listed below  
are worst-case. Precise values are provided by the timing analyzer.  
Table 20: CLB Switching Characteristics  
Speed Grade  
Description  
Combinatorial Delays  
Symbol  
6  
5  
4  
Units  
0.35  
0.57  
0.76  
0.36  
0.26  
0.26  
0.35  
0.41  
0.39  
0.63  
0.83  
0.39  
0.28  
0.28  
0.38  
0.45  
0.44  
0.72  
0.95  
0.45  
0.32  
0.32  
0.44  
0.51  
4-input function: F/G inputs to X/Y outputs  
5-input function: F/G inputs to F5 output  
5-input function: F/G inputs to X output  
FXINA or FXINB inputs to Y output via MUXFX  
FXINA input to FX output via MUXFX  
FXINB input to FX output via MUXFX  
SOPIN input to SOPOUT output via ORCY  
T
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ILO  
T
IF5  
T
IF5X  
IFXY  
T
T
T
INAFX  
INBFX  
T
SOPSOP  
Incremental delay routing through transparent latch  
to XQ/YQ outputs  
T
ns, Max  
IFNCTL  
Sequential Delays  
0.45  
0.54  
0.50  
0.59  
0.57  
0.68  
FF Clock CLK to XQ/YQ outputs  
Latch Clock CLK to XQ/YQ outputs  
Setup and Hold Times Before/After Clock CLK  
BX/BY inputs  
T
ns, Max  
ns, Max  
CKO  
T
CKLO  
0.30/–0.07  
0.30/–0.07  
0.30/–0.07  
0.19/–0.06  
0.21/–0.02  
0.33/–0.08  
0.33/–0.08  
0.33/–0.08  
0.21/–0.07  
0.23/–0.03  
0.37/–0.09  
0.37/–0.09  
0.37/–0.09  
0.24/–0.08  
0.26/–0.03  
T
/T  
ns, Min  
ns, Min  
ns, Min  
ns, Min  
ns, Min  
DICK CKDI  
DY inputs  
T
/T  
DYCK CKDY  
DX inputs  
T
T
T
/T  
DXCK CKDX  
CE input  
/T  
CECK CKCE  
SR/BY inputs (synchronous)  
Clock CLK  
T
SRCK/ SCKR  
0.61  
0.61  
0.67  
0.67  
0.77  
0.77  
Minimum Pulse Width, High  
Minimum Pulse Width, Low  
Set/Reset  
T
ns, Min  
ns, Min  
CH  
T
CL  
0.61  
1.06  
0.67  
1.17  
0.77  
1.34  
Minimum Pulse Width, SR/BY inputs  
T
ns, Min  
ns, Max  
MHz  
RPW  
Delay from SR/BY inputs to XQ/YQ outputs  
(asynchronous)  
T
RQ  
820  
750  
650  
Toggle Frequency (MHz) (for export control)  
F
TOG  
DS031-3 (v3.0) August 1, 2003  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 3 of 4  
19  
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