R
Spartan-IIE FPGA Family: Functional Description
from a PROM. A Spartan-IIE device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2). The weak pull-ups on the mode pins
make slave serial the default mode if the pins are left uncon-
nected.
After INIT
Goes High
User Load One
Configuration
Bit on Next
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK.
CCLK Rising Edge
Timing for Slave Serial mode is shown in Figure 24,
page 49.
End of
Configuration
Data File?
No
Daisy Chain
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. After an FPGA is
configured, data for the next device is sent to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Note that DOUT changes on the falling edge of CCLK for
some Xilinx families but mixed daisy chains are allowed.
Configuration must be delayed until INIT pins of all
daisy-chained FPGAs are High. For more information, see
Start-up, page 23.
Yes
To CRC Check
DS001_14_032300
Figure 18: Loading Serial Mode Configuration Data
Slave Serial Mode
The maximum amount of data that can be sent to the DOUT
pin for a serial daisy chain is 220-1 (1,048,575) 32-bit words,
or 33,554,400 bits, which is approximately 8 XC2S600E bit-
streams. The configuration bitstream of downstream
devices is limited to this size.
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing the FPGA to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 19 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
3.3V
3.3V
1.8V
3.3V
3.3V
1.8V
3.3 K
M0 M1
M2
VCCO
M0 M1
M2
VCCO
VCCINT
VCCINT
DOUT
DOUT
DIN
CCLK
Spartan-IIE
Spartan-IIE
(Slave)
(Master Serial)
VCC
Xilinx
PROM
CCLK
CLK
DATA
DIN
CE
CEO
PROGRAM
PROGRAM
DONE
RESET/OE
DONE
INIT
INIT
GND
GND
GND
PROGRAM
Notes:
DS077-2_04_061708
1. If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330Ω resistor.
Figure 19: Master/Slave Serial Configuration Circuit Diagram
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
25
Product Specification
XILINX [ XILINX, INC ]
