R
Spartan-IIE FPGA Family: Functional Description
The FPGA accepts one bit of configuration data on each ris-
ing CCLK edge. After the FPGA has been loaded, the data
for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge. The timing for Master
Serial mode is shown in Figure 25, page 49.
Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM, which feeds a serial stream of configuration
data to the FPGA’s DIN input. Figure 19 shows a Master
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-IIE device in Master Serial mode should
be connected as shown for the device on the left side. Mas-
ter Serial mode is selected by a <00x> on the mode pins
(M0, M1, M2). The PROM RESET pin is driven by INIT, and
the CE input is driven by DONE. For more information on
serial PROMs, see the Xilinx Configuration PROM data
sheets at:
Slave Parallel Mode (SelectMAP)
The Slave Parallel mode, also known as SelectMAP, is the
fastest configuration option. Byte-wide data is written into
the FPGA on the D0-D7 pins. Note that D0 is the MSB of
each byte for configuration. A BUSY flag is provided for con-
trolling the flow of data at a clock frequency above 50 MHz.
www.xilinx.com/support/documentation/configuration_proms_data_sheets.htm
Figure 20, page 27 shows the connections for two
Spartan-IIE devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
The interface is identical to the slave serial mode except
that an oscillator internal to the FPGA is used to generate
the configuration clock (CCLK). Any of a number of different
frequencies ranging from 4 to 60 MHz can be set using the
ConfigRate option in the Xilinx development software.
When selecting a CCLK frequency, ensure that the serial
PROM and any daisy-chained FPGAs are fast enough to
support the clock rate. On power-up, while the first 60 bytes
of the configuration data are being loaded, the CCLK fre-
quency is always 2.5 MHz. This frequency is used until the
ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point the frequency
changes to the selected ConfigRate. Unless a different fre-
quency is specified in the design, the default ConfigRate is
4 MHz. The frequency of the CCLK signal created by the
internal oscillator has a variance of +45%, –30% from the
specified value.
The agent controlling configuration is not shown. Typically, a
processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit read-
back. Then data can be read by deasserting WRITE. If
retention is selected, prohibit the D0-D7 pins from being
used as user I/O. See Readback, page 28.
26
www.xilinx.com
DS077-2 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
