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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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R
Spartan-IIE FPGA Family: Functional Description  
Table 11: Configuration Modes  
Preconfiguration  
CCLK  
Configuration Mode  
Pull-ups  
M0  
0
M1  
0
M2  
0
Direction  
Data Width  
Serial DOUT  
Master Serial mode  
No  
Out  
1
Yes  
Yes  
Yes  
No  
0
0
1
Slave Parallel mode  
(SelectMAP)  
0
1
0
In  
8
1
1
No  
No  
0
1
1
Boundary-Scan mode  
Slave Serial mode  
Notes:  
Yes  
No  
1
0
0
N/A  
In  
1
0
1
Yes  
No  
1
1
0
Yes  
1
1
1
1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os  
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration  
(see Answer 10504).  
2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode  
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine  
whether the unused I/Os have a pull-up, pull-down, or no resistor.  
Loading data frames  
Start-up  
Signals  
There are two kinds of pins that are used to configure  
Spartan-IIE devices: Dedicated pins perform only specific  
configuration-related functions; the other pins can serve as  
general purpose I/Os once user operation has begun.  
The memory clearing and start-up phases are the same for  
all configuration modes; however, the steps for the loading  
of data frames are different. Thus, the details for data frame  
loading are described separately in the sections devoted to  
each mode.  
The dedicated pins comprise the mode pins (M2, M1, M0),  
the configuration clock pin (CCLK), the PROGRAM pin, the  
DONE pin and the boundary-scan pins (TDI, TDO, TMS,  
TCK). Depending on the selected configuration mode,  
CCLK may be an output generated by the FPGA, or may be  
generated externally, and provided to the FPGA as an input.  
Initiating Configuration  
There are two different ways to initiate the configuration pro-  
cess: applying power to the device or asserting the PRO-  
GRAM input.  
Note that some configuration pins can act as outputs. For  
correct operation, these pins require a VCCO of 3.3V to drive  
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the  
relevant pins fall in banks 2 or 3. The CS and WRITE pins  
for Slave Parallel mode are located in bank 1.  
Configuration on power-up occurs automatically unless it is  
delayed by the user, as described in a separate section  
below. The waveform for configuration on power-up is  
shown in Configuration Switching Characteristics, page 48.  
Before configuration can begin, VCCO Bank 2 must be  
greater than 1.0V. Furthermore, all VCCINT power pins must  
be connected to a 1.8V supply. For more information on  
delaying configuration, see Clearing Configuration Memory,  
page 23.  
For a more detailed description than that given below, see  
Module 1 and XAPP176, Configuration and Readback of  
the Spartan-II and Spartan-IIE FPGA Families.  
The Process  
The sequence of steps necessary to configure Spartan-IIE  
devices are shown in Figure 16. The overall flow can be  
divided into three different phases.  
Once in user operation, the device can be re-configured  
simply by pulling the PROGRAM pin Low. The device  
acknowledges the beginning of the configuration process by  
driving DONE Low, then enters the memory-clearing phase.  
Initiating configuration  
Configuration memory clear  
22  
www.xilinx.com  
DS077-2 (v2.3) June 18, 2008  
Product Specification  
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