R
Spartan-IIE FPGA Family: Functional Description
Table 8: Boundary-Scan Instructions (Continued)
The public boundary-scan instructions are available prior to
configuration, except for USER1 and USER2. After configu-
ration, the public instructions remain available together with
any USERCODE instructions installed during the configura-
tion. While the SAMPLE/PRELOAD and BYPASS instruc-
tions are available during configuration, it is recommended
that boundary-scan operations not be performed during this
transitional period.
Boundary-Scan
Command
Binary
Code[4:0]
Description
INTEST
USERCODE
IDCODE
00111
01000
01001
01010
Enables boundary-scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of
ID Code
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
HIGHZ
Disables output pins
while enabling the
Bypass Register
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
Figure 14 is a diagram of the Spartan-IIE family boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
BYPASS
11111
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
DATA IN
IOB.T
0
1
0
sd
1
D
D
Q
Q
D
Q
LE
IOB IOB IOB IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
Bypass
Register
0
1
M
U
X
TDO
1
sd
sd
Instruction Register
D
D
Q
Q
D
Q
Q
TDI
0
LE
1
D
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
CLOCK DATA
REGISTER
SHIFT/
CAPTURE
DS001_09_032300
Figure 14: Spartan-IIE Family Boundary Scan Logic
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
19
Product Specification
XILINX [ XILINX, INC ]
