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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family: Functional Description  
Bit Sequence  
TDO.T  
TDO.O  
Bit 0 ( TDO end)  
Bit 1  
Bit 2  
The bit sequence within each IOB is: In, Out, 3-State. The  
input-only pins contribute only the In bit to the boundary  
scan I/O data register, while the output-only pins contributes  
all three bits.  
Top-edge IOBs (Right to Left)  
Left-edge IOBs (Top to Bottom)  
From a cavity-up view of the chip (as shown in the FPGA  
Editor), starting in the upper right chip corner, the boundary  
scan data-register bits are ordered as shown in Figure 15.  
MODE.I  
BSDL (Boundary Scan Description Language) files for  
Spartan-IIE family devices are available on the Xilinx web  
site at:  
Bottom-edge IOBs (Left to Right)  
http://www.xilinx.com/support/download/sp2ebsdl.htm.  
Right-edge IOBs (Bottom to Top)  
BSCANT.UPD  
Spartan-IIE FPGA boundary scan IDCODE values are  
shown in Table 9.  
(TDI end)  
DS001_10_032300  
Figure 15: Boundary Scan Bit Sequence  
Table 9: Spartan-IIE IDCODE Values  
IDCODE  
Device  
XC2S50E  
Version  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
Family  
Array Size  
0 0001 0000  
0 0001 0100  
0 0001 1000  
0 0001 1100  
0 0010 0000  
0 0010 1000  
0 0011 0000  
Manufacturer  
0000 1001 001  
0000 1001 001  
0000 1001 001  
0000 1001 001  
0000 1001 001  
0000 1001 001  
0000 1001 001  
Required  
0000 101  
0000 101  
0000 101  
0000 101  
0000 101  
0000 101  
0000 101  
1
1
1
1
1
1
1
XC2S100E  
XC2S150E  
XC2S200E  
XC2S300E  
XC2S400E  
XC2S600E  
For HDL design entry, the Xilinx FPGA development system  
provides interfaces to several synthesis design environ-  
ments.  
Development System  
Spartan-IIE FPGAs are supported by the Xilinx ISE® CAE  
tools. The basic methodology for Spartan-IIE FPGA design  
consists of three interrelated steps: design entry, imple-  
mentation, and verification. Industry-standard tools are  
used for design entry and simulation, while Xilinx provides  
proprietary architecture-specific tools for implementation.  
A standard interface-file specification, Electronic Design  
Interchange Format (EDIF), simplifies file transfers into and  
out of the development system.  
Spartan-IIE FPGAs are supported by a unified library of  
standard functions. This library contains over 400 primitives  
and macros, ranging from 2-input AND gates to 16-bit accu-  
mulators, and includes arithmetic functions, comparators,  
counters, data registers, decoders, encoders, I/O functions,  
latches, Boolean functions, multiplexers, shift registers, and  
barrel shifters.  
The Xilinx development system is integrated under the  
Xilinx Project Navigator software, providing designers with a  
common user interface regardless of their choice of entry  
and verification tools. The software simplifies the selection  
of implementation options with pull-down menus and on-line  
help.  
The design environment supports hierarchical design entry,  
with high-level designs that comprise major functional  
blocks, while lower-level designs define the logic in these  
blocks. These hierarchical design elements are automati-  
cally combined by the implementation tools. Different  
design entry tools can be combined within a hierarchical  
Several advanced software features facilitate Spartan-IIE  
FPGA design. CORE Generator™ tool functions, for exam-  
ple, include macros with relative location constraints to  
guide their placement. They help ensure optimal implemen-  
tation of common functions.  
20  
www.xilinx.com  
DS077-2 (v2.3) June 18, 2008  
Product Specification  
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