R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
I/O, L2N_YY
Bank
Pin
E5
B4
C4
A3
B3
A4
A2
Output Option
Option
XC2S400E
XC2S600E
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P_Y
I/O, L0N_Y
I/O
0
0
0
0
0
0
-
All
-
-
-
-
-
-
-
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P
I/O, L0N
I/O
All
I/O, L1P_YY
All
I/O, L1N_YY
XC2S600E
I/O
-
XC2S600E
-
-
I/O
TCK
TCK
TCK
FG676 Differential Clock Pins
P Input
N Input
Clock
GCK0
GCK1
GCK2
GCK3
Bank
Pin
AF14
AF13
A14
Name
Pin
AE14
AE13
B14
Name
4
5
1
0
GCK0, I
GCK1, I
GCK2, I
GCK3, I
I/O (DLL), L126P
I/O (DLL), L126N
I/O (DLL), L23P
I/O (DLL), L23N
A13
B13
Additional FG676 Package Pins
VCCINT Pins
H8
H19
L10
U17
J9
L17
V9
J18
T10
V18
K10
K11
U10
W19
K16
U11
-
K17
T17
W8
U16
VCCO Bank 0 Pins
C5
C8
D11
D16
K18
T18
V16
V10
T4
J10
J11
J17
K12
K14
K13
K15
VCCO Bank 1 Pins
C19
C22
H24
R17
U15
U13
R10
K9
J16
VCCO Bank 2 Pins
E24
L18
L23
M17
W24
AD19
AD5
W3
N17
AB24
AD22
AD8
AB3
E3
VCCO Bank 3 Pins
P17
T23
U18
AC16
AC11
U9
VCCO Bank 4 Pins
U14
V17
VCCO Bank 5 Pins
U12
V11
VCCO Bank 6 Pins
P10
T9
L9
VCCO Bank 7 Pins
H3
L4
M10
N10
106
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
