R
Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
Output Option
Option
XC2S400E
XC2S600E
I/O, VREF Bank 1,
L25P
1
D14
XC2S600E
All
I/O, VREF Bank 1,
L25P
I/O, VREF Bank 1,
L25P_Y
I/O, L25N
I/O
1
1
1
1
1
1
1
C14
J13
XC2S600E
-
-
-
-
-
-
-
I/O, L25N
-
I/O, L25N_Y
I/O
-
-
-
-
-
-
I/O, L24P
I/O, L24N
I/O
C13
D13
H13
B14
A14
I/O, L24P
I/O, L24N
-
I/O, L24P
I/O, L24N
I/O
I/O (DLL), L23P
GCK2, I
I/O (DLL), L23P
GCK2, I
I/O (DLL), L23P
GCK2, I
GCK3, I
0
0
0
0
0
0
0
A13
B13
E13
F13
G13
A12
B12
-
-
-
GCK3, I
I/O (DLL), L23N
-
GCK3, I
I/O (DLL), L23N
I/O
I/O (DLL), L23N
I/O
-
-
-
I/O, L22P_YY
I/O, L22N_YY
I/O, L21P
All
-
I/O, L22P_YY
I/O, L22N_YY
-
I/O, L22P_YY
I/O, L22N_YY
I/O, L21P_Y
All
-
XC2S600E
XC2S600E
-
I/O, VREF Bank 0,
L21N
All
I/O, VREF Bank 0
I/O, VREF Bank 0,
L21N_Y
I/O, L20P
I/O, L20N
I/O
0
0
0
0
0
0
0
0
D12
E12
F12
G12
H12
J12
XC2S600E
-
-
I/O, L20P
I/O, L20N
-
I/O, L20P_Y
I/O, L20N_Y
I/O
XC2S600E
-
-
I/O, L19P_YY
I/O, L19N_YY
I/O
All
All
-
-
I/O, L19P_YY
I/O, L19N_YY
-
I/O, L19P_YY
I/O, L19N_YY
I/O
-
-
I/O, L18P_YY
A11
B11
All
All
-
I/O, L18P_YY
I/O, L18P_YY
I/O, VREF Bank 0,
L18N_YY
All
I/O, VREF Bank 0,
L18N_YY
I/O, VREF Bank 0,
L18N_YY
I/O, L17P_YY
I/O, L17N_YY
I/O
0
0
0
0
0
0
0
0
0
E11
F11
C11
G11
H11
C10
A10
B10
D10
All
All
-
-
-
-
-
-
-
-
-
-
I/O, L17P_YY
I/O, L17N_YY
-
I/O, L17P_YY
I/O, L17N_YY
I/O
I/O, L16P
-
I/O, L16P
I/O, L16N
-
I/O, L16P
I/O, L16N
I/O
-
I/O, L16N
I/O
-
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
All
All
All
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
104
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
