R
Spartan-II FPGA Family: DC and Switching Characteristics
Input/Output
Standard
CTT
AGP
V
IL
V, Min
–0.5
–0.5
V, Max
V
REF
– 0.2
V
REF
– 0.2
V, Min
V
REF
+ 0.2
V
REF
+ 0.2
V
IH
V, Max
3.6
3.6
V
OL
V, Max
V
REF
– 0.4
10% V
CCO
V
OH
V, Min
V
REF
+ 0.4
90% V
CCO
I
OL
mA
8
Note (2)
I
OH
mA
–8
Note (2)
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and
junction temperature). Values apply to all Spartan-II devices
unless otherwise noted.
Global Clock Input to Output Delay for LVTTL,
with
DLL (Pin-to-Pin)
(1)
Speed Grade
All
Symbol
T
ICKOFDLL
Description
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate,
with
DLL.
Device
All
Min
-6
Max
2.9
-5
Max
3.3
Units
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
and
3. DLL output jitter is already included in the timing calculation.
4. For data
output
with different standards, adjust delays with the values shown in
For a global clock input with standards other than LVTTL, adjust delays with values from the
Global Clock Input to Output Delay for LVTTL,
without
DLL (Pin-to-Pin)
(1)
All
Min
Speed Grade
-6
Max
4.5
4.5
4.5
4.6
4.6
4.7
-5
Max
5.4
5.4
5.4
5.5
5.5
5.6
Symbol
T
ICKOF
Description
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate,
without
DLL.
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Units
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
and
3. For data
output
with different standards, adjust delays with the values shown in
For a global clock input with standards other than LVTTL, adjust delays with values from the
DS001-3 (v2.8) June 13, 2008
Product Specification
Module 3 of 4
54
XILINX [ XILINX, INC ]
