R
Spartan-II FPGA Family: DC and Switching Characteristics
(1)
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in "IOB Input Delay Adjustments for Different Standards," page 57.
Speed Grade
-6
-5
Symbol
Propagation Delays
TIOPI
Description
Device
Min
Max
Min
Max Units
Pad to I output, no delay
Pad to I output, with delay
All
All
All
-
-
-
0.8
1.5
1.7
-
-
-
1.0
1.8
2.0
ns
ns
ns
TIOPID
TIOPLI
Pad to output IQ via transparent latch,
no delay
TIOPLID
Pad to output IQ via transparent latch,
with delay
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
-
-
-
-
-
-
3.8
3.8
3.8
3.8
4.0
4.0
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.7
4.7
ns
ns
ns
ns
ns
ns
Sequential Delays
TIOCKIQ
Clock CLK to output IQ
All
-
0.7
-
0.8
ns
Setup/Hold Times with Respect to Clock CLK(2)
TIOPICK / TIOICKP Pad, no delay
IOPICKD / TIOICKPD Pad, with delay(1)
All
1.7 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.9 / 0
3.9 / 0
0.9 / 0.01
-
-
-
-
-
-
-
-
1.9 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.6 / 0
4.6 / 0
0.9 / 0.01
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
T
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
All
TIOICECK / TIOCKICE ICE input
Set/Reset Delays
TIOSRCKI
TIOSRIQ
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
All
All
All
-
-
-
1.1
1.5
9.9
-
-
-
1.2
1.7
ns
ns
ns
TGSRQ
11.7
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table "Delay Measurement Methodology," page 60.
2. A zero hold time listing indicates no hold time or a negative hold time.
DS001-3 (v2.8) June 13, 2008
Product Specification
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