R
Spartan-II FPGA Family: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard,
with
DLL (Pin-to-Pin)
Speed Grade
-6
Symbol
T
PSDLL
/ T
PHDLL
Description
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,
(1)
with DLL
Device
All
Min
1.7 / 0
-5
Min
1.9 / 0
Units
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. A zero hold time listing indicates no hold time or a negative hold time.
5. For data input with different standards, adjust the setup time delay by the values shown in
For a global clock input with standards other than LVTTL, adjust delays with values from the
Global Clock Setup and Hold for LVTTL Standard,
without
DLL (Pin-to-Pin)
Speed Grade
-6
Symbol
T
PSFD
/ T
PHFD
Description
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,
(1)
without DLL
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Min
2.2 / 0
2.2 / 0
2.2 / 0
2.3 / 0
2.4 / 0
2.4 / 0
-5
Min
2.7 / 0
2.7 / 0
2.7 / 0
2.8 / 0
2.9 / 0
3.0 / 0
Units
ns
ns
ns
ns
ns
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A zero hold time listing indicates no hold time or a negative hold time.
4. For data input with different standards, adjust the setup time delay by the values shown in
For a global clock input with standards other than LVTTL, adjust delays with values from the
DS001-3 (v2.8) June 13, 2008
Product Specification
Module 3 of 4
55
XILINX [ XILINX, INC ]
