R
Spartan-II FPGA Family: DC and Switching Characteristics
Power-On Requirements
Spartan-II FPGAs require that a minimum supply current
I
CCPO
be provided to the V
CCINT
lines for a successful
power-on. If more current is available, the FPGA can
consume more than I
CCPO
minimum, though this cannot
adversely affect reliability.
A maximum limit for I
CCPO
is not specified. Therefore the
use of foldback/crowbar supplies and fuses deserves
special attention. In these cases, limit the I
CCPO
current to a
level below the trip point for over-current protection in order
to avoid inadvertently shutting down the supply.
New
Requirements
(1)
For Devices with
Date Code 0321
or Later
Old
Requirements
(1)
For Devices with
Date Code
before 0321
Conditions
Junction
Temperature
(2)
–40°C
≤
T
J
< –20°C
–20°C
≤
T
J
< 0°C
0°C
≤
T
J
≤
85°C
85°C < T
J
≤
100°C
T
CCPO(4,5)
V
CCINT
ramp time
Notes:
Symbol
I
CCPO(3)
Description
Total V
CCINT
supply
current required
during power-on
Device
Temperature
Grade
Industrial
Industrial
Commercial
Industrial
All
Min
1.50
1.00
0.25
0.50
-
Max
-
-
-
-
50
Min
2.00
2.00
0.50
0.50
-
Max
-
-
-
-
50
Units
A
A
A
A
ms
–40°C
≤
T
J
≤
100°C
1.
2.
3.
4.
5.
6.
The date code is printed on the top of the device’s package. See the
section in Module 1.
The expected T
J
range for the design determines the I
CCPO
minimum requirement. Use the applicable ranges in the junction
temperature column to find the associated current values in the appropriate new or old requirements column according to the date
code. Then choose the highest of these current values to serve as the minimum I
CCPO
requirement that must be met. For example,
if the junction temperature for a given design is -25°C
≤
T
J
≤
75°C, then the new minimum I
CCPO
requirement is 1.5A.
If 5°C
≤
T
J
≤
90°C, then the new minimum I
CCPO
requirement is 0.5A.
The I
CCPO
requirement applies for a brief time (commonly only a few milliseconds) when V
CCINT
ramps from 0 to 2.5V.
The ramp time is measured from GND to V
CCINT
max on a fully loaded board.
During power-on, the V
CCINT
ramp must increase steadily in voltage with no dips.
For more information on designing to meet the power-on specifications, refer to the application note
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for V
OL
and V
OH
are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
Input/Output
Standard
LVTTL
(1)
LVCMOS2
PCI, 3.3V
PCI, 5.0V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
V
IL
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, Max
0.8
0.7
44% V
CCINT
0.8
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V, Min
2.0
1.7
60% V
CCINT
2.0
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
IH
V, Max
5.5
5.5
V
CCO
+ 0.5
5.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
standards meet their specifications. The selected standards
are tested at minimum V
CCO
with the respective I
OL
and I
OH
currents shown. Other standards are sample tested.
V
OL
V, Max
0.4
0.4
10% V
CCO
0.55
0.4
0.6
0.4
0.4
0.4
V
REF
– 0.6
V
REF
– 0.8
V
REF
– 0.6
V
REF
– 0.8
V
OH
V, Min
2.4
1.9
90% V
CCO
2.4
N/A
N/A
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.6
V
REF
+ 0.8
I
OL
mA
24
12
Note (2)
Note (2)
40
36
8
24
48
8
16
7.6
15.2
I
OH
mA
–24
–12
Note (2)
Note (2)
N/A
N/A
–8
–8
–8
–8
–16
–7.6
–15.2
DS001-3 (v2.8) June 13, 2008
Product Specification
Module 3 of 4
53
XILINX [ XILINX, INC ]
